Embedded Systems Design with the Atmel AVR Microcontroller Part II

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144 CHAPTER 6. TIMING SUBSYSTEM Similar to the use of the timer input system, one must first turn on the timer system and configure a physical pin as a timer output pin using special registers. In addition, one also needs to program the desired external event using another special register associated with the timer output system.To generate the signal shown in Figure 6.3, one must compute the time required between the rising and the falling edges. Suppose that the external device requires a pulse which is 2 milliseconds wide to be activated. To generate the desired pulse, one must first program the logic state for the particular pin to be low and set the time value using a special register with respect to the contents of the free running counter. As was mentioned in Section 5.2, at each clock cycle, the special register contents are compared with the contents of the free running counter and when a match occurs, the programmed logic state appears on the designated hardware pin. Once the rising edge is generated, the program then must reconfigure the event to be a falling edge (logic state low) and change the contents of the special register to be compared with the free running counter. For the particular example in Figure 6.3, let’s assume that the main clock runs at 2 MHz, the free running counter is a 16 bit counter, and the name of the special register (16 bit register) where we can put appropriate values is output timer register. To generate the desired pulse, we can put $0000 first to the output timer register, and after the rising edge has been generated, we need to change the program event to a falling edge and put $0FA0 or 4000 in decimal to the output timer register. As was the case with the input timer system module, we can use output timer system interrupts to generate the desired signals as well. 6.4.4 INDUSTRIAL IMPLEMENTATION CASE STUDY (PWM) In this section, we discuss a well-known method to control the speed of a DC motor using a pulse width modulated (PWM) signal. The underlying concept is as follows. If we turn on a DC motor and provide the required voltage, the motor will run at its maximum speed. Suppose we turn the motor on and off rapidly, by applying a periodic signal. The motor at some point can not react fast enough to the changes of the voltage values and will run at the speed proportional to the average time the motor was turned on. By changing the duty cycle, we can control the speed of a DC motor as we desire. Suppose again, we want to generate a speed profile shown in Figure 6.4. As shown in the figure, we want to accelerate the speed, maintain the speed, and decelerate the speed for a fixed amount of time. The first task necessary is again to turn on the timer system, configure a physical port, and program the event to be a rising edge. As a part of the initialization process, we need to put $0000 to the output timer register we discussed in the previous subsection. Once the rising edge is generated, the program then needs to modify the event to a falling edge and change the contents of the output timer register to a value proportional to a desired duty cycle. For example, if we want to start off with 25% duty cycle, we need to input $4000 to the register, provided that we are using a 16 bit free running counter. Once the falling edge is generated, we now need to go back and change the event to be a rising edge and the contents of the output timer counter value back to $0000. If we want
Motor Velocity Acceleration Period Pulse Width Modulated Signal Speed Profile Constant Speed Period 6.5. OVERVIEW OF THE ATMEL TIMERS 145 GND Deceleration Period Time Figure 6.4: The figure shows the speed profile of a DC motor over time when a pulse-width-modulated signal is applied to the motor. to continue to generate a 25% duty cycle signal, then we must repeat the process indefinitely. Note that we are using the time for a free running counter to count from $0000 to $FFFF as one period. Now suppose we want to increase the duty cycle to 50% over 1 sec and that the clock is running at 2 MHz. This means that the free running counter counts from $0000 to $FFFF every 32.768-milliseconds, and the free running counter will count from $0000 to $FFFF, approximately 30.51 times over the period of one second. That is, we need to increase the pulse width from $4000 to $8000 in approximately 30 turns, or approximately 546 clock counts every turn. 6.5 OVERVIEW OF THE ATMEL TIMERS The Atmel ATmega164 is equipped with a flexible and powerful three channel timing system. The timer channels are designated Timer 0,Timer 1, and Timer 2. In this section, we review the operation of the timing system in detail. We begin with an overview of the timing system features followed by a detailed discussion of timer channel 0. Space does not permit a complete discussion of the other two timing channels; we review their complement of registers and highlight their features not contained
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270 APPENDIX A. ATMEGA164 REGISTER
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272 APPENDIX A. ATMEGA164 REGISTER
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Author’s Biography STEVEN F. BARR
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296 INDEX switch debouncing, 187 sw
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Embedded Systems Design with the Atmel AVR Microcontroller Part II

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