Embedded Systems Design with the Atmel AVR Microcontroller Part II

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190 CHAPTER 7. ATMEL <strong>AVR</strong> OPERATING PARAMETERS AND INTERFACING 0 1 2 3 0 assert keypad row 0 4 5 6 7 1 assert keypad row 1 8 9 A B 2 assert keypad row 2 C D E F 3 assert keypad row 3 4 5 6 7 Vcc 10K read keypad column 0 Vcc 10K read keypad column 1 Vcc 10K read keypad column 2 Vcc 10K read keypad column 3 Key pressed by user 0 1 2 3 4 5 6 7 8 9 A B C D E F none Figure 7.4: Keypad interface. Row asserted by microcontroller 3 2 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 X 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 X 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 X 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 X Column response from keypad switch 7 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 6 5 4 1 1 0 1 0 1 0 1 1 1 1 1 1 1 0 1 0 1 0 1 1 1 1 1 1 1 0 1 0 1 0 1 1 1 1 1 1 1 0 1 0 1 0 1 1 1 1 1 1 1 1 Row/Column combination read at micro port 0xEE 0xDE 0xBE 0x7E 0xED 0xDD 0xBD 0x7D 0xEB 0xDB 0xBB 0x7B 0xE7 0xD7 0xB7 0x77 0xXF PORTx[0] PORTx[1] PORTx[2] PORTx[3] PORTx[4] PORTx[5] PORTx[6] PORTx[7] <strong>Microcontroller</strong> PORTx
VDD 1M sys reset 1.0 uF ZTT 10MHz resonator 1-(TO) PB0 2-(T1) PB1 3-(AIN0) PB2 4-(AIN1) PB3 5-(SS) PB4 6-(MOSI) PB5 7-(MISO) PB6 8-(SCK) PB7 9-RESET 10-Vcc 11-GND 12-XTAL2 13-XTAL1 14-(RXD0) PD0 15-(TXD0) PD1 16-(RXD1) PD2 17-(TXD1) PD3 18-(OC1B) PD4 19-(OC1A) PD5 20-(ICP) PD6 Vcc 10K ATmega164 PORTB Vcc 10K PORTD PORTA PORTC PA0 (ADC0)-40 PA1 (ADC1)-39 PA2 (ADC2)-38 PA3 (ADC3)-37 PA4 (ADC4)-36 PA5 (ADC5)-35 PA6 (ADC6)-34 PA7 (ADC7)-33 AREF-32 AGND-31 AVCC-30 PC7 (TOSC2)-29 PC6 (TOSC1)-28 PC5-27 PC4-26 PC3-25 PC2-24 PC1-23 PC0-22 PD7 (OC2)-21 Vcc 10K 4 5 6 7 0 1 2 3 4 5 6 7 8 9 A B C D E F Figure 7.5: Hexadecimal keypad interface to microcontroller. Vcc 10K 0 1 2 3 7.3. INPUT DEVICES 191 VDD
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Embedded Systems Design with the At
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iv An Introduction to Logic Circuit
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Copyright © 2010 by Morgan & Clayp
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ABSTRACT This textbook provides pra
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x CONTENTS 7 6.9.3 Input Capture Mo
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xii CONTENTS A 8.5.3 Circuit diagra
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Preface In 2006 Morgan & Claypool P
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138 CHAPTER 6. TIMING SUBSYSTEM x(t
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240 CHAPTER 8. SYSTEM LEVEL DESIGN
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270 APPENDIX A. ATMEGA164 REGISTER
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272 APPENDIX A. ATMEGA164 REGISTER
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274 APPENDIX B. ATMEGA164 HEADER FI
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Author’s Biography STEVEN F. BARR
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296 INDEX switch debouncing, 187 sw
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