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Embedded Systems Design with the Atmel AVR Microcontroller Part II

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156 CHAPTER 6. TIMING SUBSYSTEM<br />

6.7.1.5 Input Capture Register 1 (ICR1H/ICR1L)<br />

ICR1 is a 16-bit register used to capture <strong>the</strong> value of <strong>the</strong> TCNT1 register when a desired edge on<br />

ICP1 pin has occurred.<br />

6.7.1.6 Timer/Counter Interrupt Mask Register 1 (TIMSK1)<br />

Timer 1 uses <strong>the</strong> Timer/Counter 1 Output Compare Match Interrupt Enable (OCIE1A/1B) bits,<br />

<strong>the</strong> Timer/Counter 1 Overflow Interrupt Enable (TOIE1) bit, and <strong>the</strong> Timer/Counter 1 Input<br />

Capture Interrupt Enable (IC1E1) bit.When <strong>the</strong> OCIE1A/B bit and <strong>the</strong> I-bit in <strong>the</strong> Status Register<br />

are both set to one, <strong>the</strong> Timer/Counter 1 Compare Match interrupt is enabled. When <strong>the</strong> OIE1 bit<br />

and <strong>the</strong> I-bit in <strong>the</strong> Status Register are both set to one, <strong>the</strong> Timer/Counter 1 Overflow interrupt<br />

is enabled. When <strong>the</strong> IC1E1 bit and <strong>the</strong> I-bit in <strong>the</strong> Status Register are both set to one, <strong>the</strong><br />

Timer/Counter 1 Input Capture interrupt is enabled.<br />

6.7.1.7 Timer/Counter Interrupt Flag Register (TIFR1)<br />

Timer 1 uses <strong>the</strong> Output Compare Flag 1 A/B (OCF1A/B) which sets for an output compare<br />

A/B match. Timer 1 also uses <strong>the</strong> Timer/Counter 1 Overflow Flag (TOV1) which sets when<br />

Timer/Counter 1 overflows. Timer Channel 1 also uses <strong>the</strong> Timer/Counter 1 Input Capture Flag<br />

(ICF1) which sets for an input capture event.<br />

6.8 TIMER 2<br />

Timer 2 is ano<strong>the</strong>r 8-bit timer channel similar to Timer 0. The Timer 2 channel block diagram is<br />

provided in Figure 6.13. Its registers are summarized in Figure 6.14.<br />

6.8.0.8 Timer/Counter Control Register A and B (TCCR2A and B)<br />

The TCCR2A and B register bits are used to:<br />

Select <strong>the</strong> operational mode of Timer 2 using <strong>the</strong> Waveform Mode Generation (WGM2[2:0])<br />

bits,<br />

Determine <strong>the</strong> operation of <strong>the</strong> timer <strong>with</strong>in a specific mode <strong>with</strong> <strong>the</strong> Compare Match Output<br />

Mode (COM2A[1:0] and B) bits, and<br />

Select <strong>the</strong> source of <strong>the</strong> Timer 2 clock using Clock Select (CS2[2:0]) bits.<br />

The bit settings for <strong>the</strong> TCCR2A and B registers are summarized in Figure 6.15.<br />

6.8.0.9 Timer/Counter Register(TCNT2)<br />

The TCNT2 is <strong>the</strong> 8-bit counter for Timer 2.<br />

6.8.0.10 Output Compare Register A and B (OCR2A and B)<br />

The OCR2A and B registers hold a user-defined 8-bit value that is continuously compared to <strong>the</strong><br />

TCNT2 register.

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