Embedded Systems Design with the Atmel AVR Microcontroller Part II
Embedded Systems Design with the Atmel AVR Microcontroller Part II
Embedded Systems Design with the Atmel AVR Microcontroller Part II
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Mode<br />
0<br />
1<br />
2<br />
3<br />
4<br />
5<br />
6<br />
7<br />
8<br />
9<br />
10<br />
11<br />
12<br />
13<br />
14<br />
15<br />
WGM[13:12:11:10]<br />
0000<br />
0001<br />
0010<br />
0011<br />
0100<br />
0101<br />
0110<br />
0111<br />
1000<br />
1001<br />
1010<br />
1011<br />
1100<br />
1101<br />
1110<br />
1111<br />
CS0[2:0] Clock Source<br />
000 None<br />
001 clkI/0 010 clkI/0 /8<br />
011 clkI/0 /64<br />
100 clkI/0 /8clkI/0 /256<br />
101 clkI/0 /8clkI/0 /1024<br />
110 External clock on T0 (falling edge trigger)<br />
111 External clock on T1 (rising edge trigger)<br />
Mode<br />
Normal<br />
PWM, Phase Correct, 8-bit<br />
PWM, Phase Correct, 9-bit<br />
PWM, Phase Correct, 10-bit<br />
CTC<br />
Fast PWM, 8-bit<br />
Fast PWM, 9-bit<br />
Fast PWM, 10-bit<br />
PWM, Phase & Freq Correct<br />
PWM, Phase & Freq Correct<br />
PWM, Phase Correct<br />
PWM, Phase Correct<br />
CTC<br />
Reserved<br />
Fast PWM<br />
Fast PWM<br />
PWM, Phase Correct, Phase & Freq Correct<br />
COMx[1:0]<br />
00<br />
01<br />
10<br />
11<br />
6.7. TIMER 1 155<br />
Clock Select<br />
Timer/Counter 1 Control Register B (TCCR1B)<br />
ICNC1 ICES1 --- WGM13 WGM12 CS12 CS11 CS10<br />
7<br />
0<br />
Timer/Counter 1 Control Register A (TCCR1A)<br />
COM1A1 COM1A0 COM1B1 COM1B0 --- --- WGM11 WGM10<br />
7<br />
0<br />
Waveform Generation Mode<br />
Normal, CTC<br />
COMx[1:0] Description<br />
00 Normal, OC1A/1B disconnected<br />
01 Toggle OC1A/1B on compare match<br />
10 Clear OC1A/1B on compare match<br />
11 Set OC1A/1B on compare match<br />
Figure 6.12: TCCR1A and TCCR1B registers.<br />
Fast PWM<br />
COMx[1:0]<br />
00<br />
01<br />
10<br />
11<br />
Description<br />
Normal, OC0 disconnected<br />
WGM1[3:0] = 9 or 14: toggle OCnA<br />
on compare match, OCnB disconnected<br />
WGM1[3:0]= o<strong>the</strong>r settings,<br />
OC1A/1B disconnected<br />
Clear OC0 on compare match<br />
when up-counting. Set OC0<br />
on compare match when<br />
down counting<br />
Set OC0 on compare match<br />
when up-counting. Clear OC0<br />
on compare match when<br />
down counting.<br />
Description<br />
Normal, OC1A/1B disconnected<br />
WGM1[3:0] = 9 or 11, toggle OC1A on<br />
compare match OC1B disconnected<br />
WGM1[3:0] = o<strong>the</strong>r settings,<br />
OC1A/1B disconnected<br />
Clear OC1A/1B on compare match,<br />
set OC1A/1B on Compare Match when<br />
down counting<br />
Set OC1A/1B on compare match when<br />
upcounting. Clear OC1A/1B on Compare<br />
Match when upcounting
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