Predictive Control of Three Phase AC/DC Converters

3.2. VOLTAGE ORIENTED CONTROL 19
rejection performance in transient states. Equations (3.1) and (3.2) describe PI
controller proportional gain K C and its time constant T IC :
K C =
T RL
2τ t K RL
(3.1)
T IC = 4τ t (3.2)
where: T RL = L R , K RL = 1 R
is time constant and gain of choke mathematical
model respectively, and τ t is sum of the small time constants defined as:
τ t = T s + T P W M (3.3)
where: T s is sampling time, and T P W M = 1 2 T s is PWM generation time delay.
Figure 3.3 shows block diagram of active current control loop, where τ 0 is
transistors dead time.
U Ldist
I dref
I dreff I Lderr K C (sT IC +1) U dref K VSC e -sτ 0
1
K RL I Ld
sT fC +1
Prefilter
-
I Ld
sT IC
sτ t +1
sT RL +1
PI S&H, VSC Input Choke
-
Figure 3.3: Block diagram of active current I Ld control loop in synchronous
rotating reference coordinates with prefilter
(a)
Step Response
(b)
Step Response
1.5
From: I dref
To: I d
1.5
From: I dref
To: I d
System: dq_PI_c_1
I/O: I_{dref} to I_{d}
Peak amplitude: 1.41
Overshoot (%): 41.1
At time (sec): 0.000849
System: dq_PI_c_1
I/O: I_{dref} to I_{d}
Peak amplitude: 1.07
Overshoot (%): 7.19
At time (sec): 0.00148
1
1
Amplitude
0.5
System: dq_PI_c_1
I/O: I_{dref} to I_{d}
Rise Time (sec): 0.000316
System: dq_PI_c_1
I/O: I_{dref} to I_{d}
Settling Time (sec): 0.00247
Amplitude
0.5
System: dq_PI_c_1
I/O: I_{dref} to I_{d}
Rise Time (sec): 0.000699
System: dq_PI_c_1
I/O: I_{dref} to I_{d}
Settling Time (sec): 0.00201
0
0 0.5 1 1.5 2 2.5 3 3.5
Time (sec)
x 10 −3
0
0 0.5 1 1.5 2 2.5 3 3.5
Time (sec)
x 10 −3
Figure 3.4: Step response of active current control loop in VOC: (a) without
prefilter, (b) with prefilter
However, symmetry optimum design method gives 43% overshoot of tracking
error (Fig. 3.4 (a)), so an additional block with prefilter T fC on referenced current
value is used.
T fC = 4τ t (3.4)