Control and Design of Microgrid Components - Power Systems ...

works with an internal voltage level that can be ± 3.3 V or below and the internal oscillator can
generate a frequencies up to 40MHz.
The basic concept in the DSP implementing architecture is that there is a main routine that is
executed once every period of the switching frequency, 4kHz. This routine implements the
control and the gate pulse generator. The Interrupt controller is the overseeing scheduling
manager that decides when a program starts running according to a preassigned priority. Figure
6.8 shows the priority of the programs that are running inside the DSP.
Interrupt
Controller
Microsource Control
and Gate Pulse
Generator
Higher
Priority
NOP
Figure 6.8 Interrupt Routine Queue.
The lowest priority program is a No Operation (NOP) routine, substantially it is a main function
with an empty body. The higher priority program returns control to the Interrupt controller after
it is done. When the NOP routine ends, the Interrupt controller immediately starts it again: in this
case the processor is kept in a stand-by, or busy-wait state. NOP has the lowest priority and can
be interrupted at any time.
The Interrupt control will generate a request to run the control block operation and gate pulse
generation routine four thousand times every second. In this way, gate pulses are generated at a
frequency of 4kHz: this is the frequency at which switching positions change. As soon as the
gate pulses calculation is active the NOP is frozen in time and the processor stores the position in
memory from where it was interrupted. The Interrupt control will generate a request to run the
NOP routine from exactly the point where it was stopped as soon as the routine that implements
the control and pulse generation has returned from execution.
6.4 Gate Pulse Implementation with Space Vector Modulation
This section describes the implementation based on the synthesization of a desired voltage
vector. This operation results in a constant switching frequency and is typically referred in the
literature as space vector modulation technique.
The inverter is represented in Figure 6.9: it is the simplest configuration possible, with one single
level of six power electronic devices connected to a DC ideal voltage source. The gates of the
silicon devices can be controlled independently, but there are some constraints that limit the
choices on the possible positions. For instance, two switches on the same leg (such as g 1 and
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