User Manual

List of Tables
Table 1 – Jumper Description..............................................................................................................................................................................................10
Table 2: S1 Dipswitch Configuration Settings..................................................................................................................................................................60
Table 3: HyperTerminal Main Menu Options..................................................................................................................................................................61
Table 4: HyperTerminal Interactive Configuration Menu Options..............................................................................................................................63
Table 5 - FPGA Configuration Modes ...............................................................................................................................................................................73
Table 6 - FPGA configuration file sizes .............................................................................................................................................................................74
Table 7 - Connection between Configuration FPGA/MCU..........................................................................................................................................75
Table 8 - FPGA JTAG connection to Configuration FPGA .........................................................................................................................................77
Table 9 - Clocking inputs to the FPGA’s...........................................................................................................................................................................78
Table 10 - Clock Source Signals...........................................................................................................................................................................................81
Table 11 - RoboClock Configuration Signals ....................................................................................................................................................................84
Table 12 - Connection between FPGA and External PPC Oscillator ..........................................................................................................................90
Table 13 - Connection between FPGA’s and DDR PLL Clock Drivers......................................................................................................................92
Table 14 - Connection between FPGA and External PPC Oscillator ..........................................................................................................................93
Table 15 - Connections between FPGA’s and Rocket IO Clock Synthesizers............................................................................................................95
Table 16 - PPC Reset .............................................................................................................................................................................................................98
Table 17 - Connection between FPGA and SRAM .......................................................................................................................................................103
Table 18 - Connection between FPGA’s and DDR SDRAM’s ...................................................................................................................................123
Table 19 - Connections between FPGA and SMA Connectors...................................................................................................................................144
Table 20 - RocketIO Performance ....................................................................................................................................................................................146
Table 21 - CPU Debug connection to FPGA .................................................................................................................................................................148
Table 22 - Combined CPU Trace/Debug connection to FPGA.................................................................................................................................150
Table 23 - CPLD LED's......................................................................................................................................................................................................152
Table 24 - MCU LED's .......................................................................................................................................................................................................153
Table 25 – FPGA A GPIO LED's....................................................................................................................................................................................153
Table 26 - PCI to FPGA Connections .............................................................................................................................................................................156
Table 27 - Present Signal Definition .................................................................................................................................................................................161
Table 28 - M66EN and PCIXCAP Encoding.................................................................................................................................................................162
Table 29 – Voltage Indicators ............................................................................................................................................................................................165
Table 30 - External Power Connections...........................................................................................................................................................................172
Table 31 - Connection between FPGA and the Daughter Card Headers ..................................................................................................................174
Table 32: bar_write_byte Arguments.............................................................................................................................................................................213
Table 33: bar_write_word Arguments ...........................................................................................................................................................................214
Table 34: bar_write_dword Arguments.........................................................................................................................................................................215
Table 35: bar_read_byte Arguments..............................................................................................................................................................................216
Table 36: bar_read_word Arguments ............................................................................................................................................................................217
Table 37: bar_read_dword Arguments..........................................................................................................................................................................218
Table 38: dma_buffer_allocate Arguments..................................................................................................................................................................219
Table 39: dma_buffer_free Arguments..........................................................................................................................................................................220
Table 40: dma_write_dword Arguments ......................................................................................................................................................................221
Table 41: dma_read_dword Arguments........................................................................................................................................................................222
Table 42: pci_rdwr Arguments ........................................................................................................................................................................................223
Table 43: DeviceIoControl Arguments .........................................................................................................................................................................225