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INTRODUCTION TO VIRTEX-II PRO AAND ISE • Read FPGA F Revision • Display Vendor and Device ID • Set PCI Device and Function Number • Display all configured PCI devices • Various loops for PCI device-function and ID numbers • Write and Read Configuration DWORD • Write DWORD, Read DWORD and Write/Read DWORD (Same Address) • BAR Memory Fill, Write and Display • Configure/Save BAR’s from/to a file More information coming soon. DN6000K10PCI <strong>User</strong> Guide www.dinigroup.com 26
INTRODUCTION TO VIRTEX-II PRO AAND ISE Chapter 4 Introduction to Virtex-II Pro and ISE 1 Virtex-II Pro The Virtex-II Pro FPGA solution is the most technically sophisticated silicon and software product development in the history of the programmable logic industry. The goal was to revolutionize system architecture “from the ground up.” To achieve that objective, the best circuit engineers and system architects from IBM, Mindspeed, and Xilinx co developed the world's most advanced FPGA silicon product. Leading teams from top embedded systems companies worked together with Xilinx software teams to develo p the systems software and IP solutions that enabled new system architecture paradigm. The result is the first FPGA solution capable of implementing high performance system-on-a-chip designs previously the exclusive domain of custom ASICs, yet with the flex ibility and low development cost of programmable logic. The Virtex-II Pro family marks the first paradigm change from programmable logic to programmable systems, with profound implications for leading-edge system architectures in networking applications, deeply embedded systems, and digital signal processing system s. It allows custom user-defined system architectures to be synthesized, nextgeneration connectivity standards to be seamlessly bridged, and complex hardware and software systems to be co-developed rapidly with in-system debug at system speeds. Together, these capabilities usher in the next programmable logic revolution. 1.1 Summary of Virtex-II Pro Features The Virtex-II Pro has an impressive collection of both programmable logic and hard IP that has historically been the domain of the ASICs. • High-performance FPGA solution including: o Up to twenty-four RocketIO embedded multi-gigabit transceiver blocks (based on Mindspeed's SkyRail technology) DN6000K10PCI <strong>User</strong> Guide www.dinigroup.com 27
Page 1 and 2: THE DINI GROUP LOGIC Emulation Sour
Page 3 and 4: Table of Contents ABOUT THIS MANUAL
Page 5 and 6: 4.6 Power PC (PPC) Clock - Sytem Cl
Page 7 and 8: 2.11.1 Description ................
Page 9 and 10: Figure 54 - Assembly drawing for th
Page 11 and 12: ABOUT THIS MANUAL Chapter 1 About T
Page 13 and 14: ABOUT THIS MANUAL Convention Meanin
Page 15 and 16: ABOUT THIS MANUAL Samir Palnitkar,
Page 17 and 18: GETTING STARTED Virtex-II Pro FPGA
Page 19 and 20: GETTING STARTED Figure 2 - Default
Page 21 and 22: GETTING STARTED Jumper Installed Si
Page 23 and 24: GETTING STARTED 3.5 PPC RS232 Port
Page 25 and 26: GETTING STARTED by The Dini Group.
Page 27 and 28: GETTING STARTED 7. The AETEST Test
Page 29 and 30: INTRODUCTION TO VIRTEX-II PRO AAND
Page 35: INTRODUCTION TO VIRTEX-II PRO AAND
Page 45 and 46: INTRODUCTION TO THE SOFTWARE TOOLS
Page 57 and 58: PROGRAMMING/CONFIGURING THE HARDWAR
Page 75 and 76: 1 BOARD HARDWARE Chapter 7 Board Ha
Page 77 and 78: BOARD HARDWARE • ~5900 Kbits of B
Page 79 and 80: BOARD HARDWARE MCU_A0 MCU_A1 MCU_A2
Page 81 and 82: BOARD HARDWARE • Receive Data TXD
Page 83 and 84: BOARD HARDWARE +3.3V +3.3V J6 1 2 3
Page 85 and 86: BOARD HARDWARE SM_CLE SM_ALE SM_WEn
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BOARD HARDWARE Table 8 - FPGA JTAG
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BOARD HARDWARE USER_BCLKp U16.AP21
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BOARD HARDWARE DDR_FCLKp U54.AT21 U
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BOARD HARDWARE Eighteen configurabl
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BOARD HARDWARE Signal Name Descript
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BOARD HARDWARE Signal Name Descript
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BOARD HARDWARE 4.3.5 Customizing th
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BOARD HARDWARE positive clock and t
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BOARD HARDWARE DDR_DCLKn U35.AU21 U
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BOARD HARDWARE Figure 29 - REFCLK/B
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BOARD HARDWARE +1.5V +2.5V +3.3V +5
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BOARD HARDWARE SRAM1_A0 SRAM1_A1 SR
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BOARD HARDWARE Figure 33 - SSRAM Pi
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BOARD HARDWARE 6.1.2 SSRAM Clocking
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BOARD HARDWARE Signal Name SRAM Pin
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BOARD HARDWARE 6.2 DDR SDRAM Double
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BOARD HARDWARE SSTL2 Class 1 termin
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BOARD HARDWARE Table 18 - Connectio
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BOARD HARDWARE Signal Name FPGA Pin
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BOARD HARDWARE The PowerPC 405 CPU
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BOARD HARDWARE Signal Name Device L
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BOARD HARDWARE power to the DN6000k
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BOARD HARDWARE Signal Name Connecto
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BOARD HARDWARE 10.2.3 Further Infor
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BOARD HARDWARE J2 +3.3V TP1 +12V +1
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BOARD HARDWARE DN6000K10PCI User Gu
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BOARD HARDWARE 12.2 DN3000K10SD Dau
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BOARD HARDWARE and the IDT74LVC1624
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BOARD HARDWARE 12.2.3 Unbuffered IO
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BOARD HARDWARE Daughter Card Connec
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BOARD HARDWARE The DN6000K10PCI PWB
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FPGA A Start End Address Read / Des
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FPGA B Start Address End Address Re
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FPGA D Start End Address Read / Des
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FPGA F Start End Address Read / Des
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Appendix B - AETEST 1 AETEST Instal
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Follow the procedures listed below
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2 AETEST Basic C++ Functions The AE
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2.3 bar_write_dword bar_write_dword
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2.5 bar_read_word bar_read_word is
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2.7 dma_buffer_allocate dma_buffer_
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2.9 dma_write_dword dma_write_dword
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2.11 pci_rdwr pci_rdwr is a functio
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2.12 DeviceIoControl DeviceIoContro
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2.12.5 Derived Functions The follow
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