User Manual

INTRODUCTION TO VIRTEX-II PRO AAND ISE
(4) Test Address Space – this will write the specified value to a given address
range, read it back, and check the results for errors. Note: some memory
addresses cannot be written to, and will return errors. Please check the
FPGA memory maps in Appendix A for clarification.
(5) Display Address Space – coming soon!
(6) Test DDR (through PPC’s) – tests an FPGA’s DDR by using the PPC
built into each FPGA.
(7) Test FLASH (through PPC’s) – tests an FPGA’s flash by using the PPC
built into each FPGA.
(8) Test SRAM (through PPC’s) – tests an FPGA’s SRAM by using the PPC
built into each FPGA.
(9) Test Internal Registers – coming soon!
(10) Test Interconnect – coming soon!
(11) Test ALL (through PPC’s) – tests an FPGA’s DDR, flash, and SRAM by
using the PPC built into each FPGA.
(12) Display Memory Map – coming soon!
1.1.8 Settings/Info Menu
The Settings/Info Menu has the following options
(1) Set FPGA RocketIO CLK Frequency – When the DN6000k10PCI is first
powered up the RocketIO CLK inputs to the FPGAs are inactive. The
RocketIO CLK Inputs are connected to the following FPGA Differential
CLK inputs on all FPGAs: F21/G21 and AT21/AU21. This menu option
allows the user to specify what frequency the RocketIO CLKs should be set at
for each FPGA. The supported frequency range is 31.25MHz – 700MHz.
After selecting this option, a pop-uand then what frequency you want. Check the log window to verify what
window will ask which FPGA’s RocketIO
Frequency you want to set (or you can choose to set all to the same frequency),
frequency the CLKs were actually set at.
(2) Change Text Editor – This options allows the user to select a text editor to use
(the default editor is notepad).
(3) FPGA Stuffing Information – This option will display the type of FPGAs that
are stuffed on the DN6000k10PCI.
DN6000K10PCI User Guide www.dinigroup.com 24