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ABOUT THIS MANUAL 2 Additional Resources For additional information, go to http://www.dinigroup.com/. The following table lists some of the resources you can access from this website. You can also directly access these resources using the provided URLs. Resource User Manual Dini Group Web Site Data Book E-Mail Phone Support FAQ Description/URL This is the main source of technical information. The manual should contain most of the answers to your questions The web page will contain the latest manual, application notes, FAQ, articles, and any device errata and manual addenda. Please visit and bookmark: http://www.dinigroup.com Pages from The Programmable Logic Data Book, which contains device-specific information on Xilinx device characteristics, including readback, boundary scan, configuration, length count, and debugging http://direct.xilinx.com/bvdocs/publications/ds083.pdf You may direct questions and feedback to the Dini Group using this e-mail address: support@dinigroup.com Call us at 858.454.3419 during the hours of 8:00am to 5:00pm Pacific Time. The download section of the web page contains a document called DN6000K10PCI Frequently Asked Questions (FAQ). This document is periodically updated with information that may not be in the User’s Manual. 3 Conventions This document uses the following conventions. An example illustrates each convention. 3.1 Typographical The following typographical conventions are used in this document: Convention Meaning or Use Example Courier font Messages, prompts, and program files that the system displays speed grade: - 100 DN6000K10PCI User Guide www.dinigroup.com 2
ABOUT THIS MANUAL Convention Meaning or Use Example Courier bold Garamond bold Italic font Braces [ ] Braces { } Vertical bar | Vertical ellipsis - - - Horizontal ellipsis . . . Prefix “0x” or suffix “h” Literal commands that you enter in a syntactical statement Commands that you select from a menu Keyboard shortcuts Variables in a syntax statement for which you must supply values References to other manuals Emphasis in text An optional entry or parameter. However, in bus specifications, such as bus[7:0], they are required. A list of items from which you must choose one or more Separates items in a list of choices Repetitive material that has been omitted Repetitive material that has been omitted Indicates hexadecimal notation ngdbuild design_name File Open Ctrl+C ngdbuild design_name See the Development System Reference Guide for more information. If a wire is drawn so that it overlaps the pin of a symbol, the two nets are not connected. ngdbuild [option_name] design_name lowpwr ={on|off} lowpwr ={on|off} IOB #1: Name = QOUT’ IOB #2: Name = CLKIN’ - - allow block block_name loc1 loc2 ... locn; Read from address 0x00110373, returned 4552494h Letter “#” or “_n” Signal is active low INT# is active low fpga_inta_n is active low DN6000K10PCI User Guide www.dinigroup.com 3
Page 1 and 2: THE DINI GROUP LOGIC Emulation Sour
Page 3 and 4: Table of Contents ABOUT THIS MANUAL
Page 5 and 6: 4.6 Power PC (PPC) Clock - Sytem Cl
Page 7 and 8: 2.11.1 Description ................
Page 9 and 10: Figure 54 - Assembly drawing for th
Page 11: ABOUT THIS MANUAL Chapter 1 About T
Page 15 and 16: ABOUT THIS MANUAL Samir Palnitkar,
Page 17 and 18: GETTING STARTED Virtex-II Pro FPGA
Page 19 and 20: GETTING STARTED Figure 2 - Default
Page 21 and 22: GETTING STARTED Jumper Installed Si
Page 23 and 24: GETTING STARTED 3.5 PPC RS232 Port
Page 25 and 26: GETTING STARTED by The Dini Group.
Page 27 and 28: GETTING STARTED 7. The AETEST Test
Page 29 and 30: INTRODUCTION TO VIRTEX-II PRO AAND
Page 45 and 46: INTRODUCTION TO THE SOFTWARE TOOLS
Page 57 and 58: PROGRAMMING/CONFIGURING THE HARDWAR
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PROGRAMMING/CONFIGURING THE HARDWAR
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1 BOARD HARDWARE Chapter 7 Board Ha
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BOARD HARDWARE • ~5900 Kbits of B
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BOARD HARDWARE MCU_A0 MCU_A1 MCU_A2
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BOARD HARDWARE • Receive Data TXD
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BOARD HARDWARE +3.3V +3.3V J6 1 2 3
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BOARD HARDWARE SM_CLE SM_ALE SM_WEn
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BOARD HARDWARE Table 8 - FPGA JTAG
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BOARD HARDWARE USER_BCLKp U16.AP21
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BOARD HARDWARE DDR_FCLKp U54.AT21 U
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BOARD HARDWARE Eighteen configurabl
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BOARD HARDWARE Signal Name Descript
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BOARD HARDWARE Signal Name Descript
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BOARD HARDWARE 4.3.5 Customizing th
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BOARD HARDWARE positive clock and t
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BOARD HARDWARE DDR_DCLKn U35.AU21 U
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BOARD HARDWARE Figure 29 - REFCLK/B
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BOARD HARDWARE +1.5V +2.5V +3.3V +5
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BOARD HARDWARE SRAM1_A0 SRAM1_A1 SR
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BOARD HARDWARE Figure 33 - SSRAM Pi
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BOARD HARDWARE 6.1.2 SSRAM Clocking
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BOARD HARDWARE Signal Name SRAM Pin
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BOARD HARDWARE 6.2 DDR SDRAM Double
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BOARD HARDWARE SSTL2 Class 1 termin
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BOARD HARDWARE Table 18 - Connectio
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BOARD HARDWARE Signal Name FPGA Pin
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BOARD HARDWARE The PowerPC 405 CPU
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BOARD HARDWARE Signal Name Device L
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BOARD HARDWARE power to the DN6000k
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BOARD HARDWARE Signal Name Connecto
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BOARD HARDWARE 10.2.3 Further Infor
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BOARD HARDWARE J2 +3.3V TP1 +12V +1
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BOARD HARDWARE DN6000K10PCI User Gu
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BOARD HARDWARE 12.2 DN3000K10SD Dau
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BOARD HARDWARE and the IDT74LVC1624
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BOARD HARDWARE 12.2.3 Unbuffered IO
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BOARD HARDWARE Daughter Card Connec
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BOARD HARDWARE The DN6000K10PCI PWB
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FPGA A Start End Address Read / Des
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FPGA B Start Address End Address Re
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FPGA D Start End Address Read / Des
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FPGA F Start End Address Read / Des
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Appendix B - AETEST 1 AETEST Instal
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Follow the procedures listed below
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2 AETEST Basic C++ Functions The AE
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2.3 bar_write_dword bar_write_dword
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2.5 bar_read_word bar_read_word is
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2.7 dma_buffer_allocate dma_buffer_
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2.9 dma_write_dword dma_write_dword
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2.11 pci_rdwr pci_rdwr is a functio
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2.12 DeviceIoControl DeviceIoContro
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2.12.5 Derived Functions The follow
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