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LOGIC EMULATION SOURCE DN6000K10PCI <strong>User</strong> <strong>Manual</strong> Version 1.2 © The Dini Group 1010 Pearl Street • Suite 6 La Jolla, CA92037 Phone 858.454.3419 • Fax 858.454.1279 support@dinigroup.com www.dinigroup.com
Table of Contents ABOUT THIS MANUAL ......................................................................................................................................................................................................... 1 1 MANUAL CONTENTS.................................................................................................................................................................................................... 1 2 ADDITIONAL RESOURCES............................................................................................................................................................................................ 2 3 CONVENTIONS ............................................................................................................................................................................................................. 2 3.1 Typographical ......................................................................................................................................................................................................... 2 3.2 Online Document..................................................................................................................................................................................................... 4 4 RELEVANT INFORMATION ........................................................................................................................................................................................... 4 GETTING STARTED .............................................................................................................................................................................................................. 6 1 PRECAUTION................................................................................................................................................................................................................ 6 2 THE DN6000K10PCI LOGIC EMULATION KIT ......................................................................................................................................................... 6 3 INSTALLATION INSTRUCTIONS .................................................................................................................................................................................... 8 3.1 Jumper Setup ........................................................................................................................................................................................................... 8 3.2 Jumper Description............................................................................................................................................................................................... 10 3.3 Switch Setup and Description ............................................................................................................................................................................... 12 3.4 Oscillator Setup..................................................................................................................................................................................................... 12 3.5 PPC RS232 Port Setup.......................................................................................................................................................................................... 13 3.6 Powering ON the DN6000K10PCI....................................................................................................................................................................... 13 4 PLAYING WITH YOUR DN6000K10PCI VIA AETEST............................................................................................................................................... 14 5 PLAYING WITH YOUR DN6000K10PCI VIA THE USB INTERFACE............................................................................................................................ 17 6 PLAYING WITH YOUR DN6000K10PCI VIA THE PPC’S............................................................................................................................................ 18 INTRODUCTION TO USB CONTROLLER SOFTWARE ............................................................................................................................................. 19 1 EXPLORING THE SOFTWARE TOOLS .......................................................................................................................................................................... 19 1.1 USBController....................................................................................................................................................................................................... 19 1.1.1 Getting Started with USBController............................................................................................................................................................. 20 1.1.2 Basic Menu Operations................................................................................................................................................................................. 20 1.1.3 Enable/Disable USB to FPGA Communication........................................................................................................................................... 21 1.1.4 File Menu .................................................................................................................................................................................................. 22 1.1.5 Edit Menu...................................................................................................................................................................................................... 22 1.1.6 FPGA Configuration Menu........................................................................................................................................................................... 22 1.1.7 FPGA MemoryMenu .................................................................................................................................................................................... 23 1.1.8 Settings/Info Menu........................................................................................................................................................................................ 24 1.2 PCI AETEST Application...................................................................................................................................................................................... 25 INTRODUCTION TO VIRTEX-II PRO AND ISE ............................................................................................................................................................ 27 1 VIRTEX-II PRO........................................................................................................................................................................................................... 27 1.1 Summary of Virtex-II Pro Features ...................................................................................................................................................................... 27 1.2 PowerPC 405 Core ........................................................................................................................................................................................... 28 1.3 RocketIO 3.125 Gbps Transceivers ...................................................................................................................................................................... 28 1.4 Virtex-II FPGA Fabric.......................................................................................................................................................................................... 29 2 FOUNDATION ISE 6.1I ............................................................................................................................................................................................... 31 2.1 Foundation Features............................................................................................................................................................................................. 31 2.1.1 Design Entry.................................................................................................................................................................................................. 31 2.1.2 Synthesis........................................................................................................................................................................................................ 32 2.1.3 Implementation and Configuration............................................................................................................................................................... 32 2.1.4 Board Level Integration ................................................................................................................................................................................ 33 3 VIRTEX-II PRO DEVELOPER’S KIT ............................................................................................................................................................................ 33 INTRODUCTION TO THE REFERENCE DESIGN ........................................................................................................................................................ 35
Page 1: THE DINI GROUP LOGIC Emulation Sour
Page 5 and 6: 4.6 Power PC (PPC) Clock - Sytem Cl
Page 7 and 8: 2.11.1 Description ................
Page 9 and 10: Figure 54 - Assembly drawing for th
Page 11 and 12: ABOUT THIS MANUAL Chapter 1 About T
Page 13 and 14: ABOUT THIS MANUAL Convention Meanin
Page 15 and 16: ABOUT THIS MANUAL Samir Palnitkar,
Page 17 and 18: GETTING STARTED Virtex-II Pro FPGA
Page 19 and 20: GETTING STARTED Figure 2 - Default
Page 21 and 22: GETTING STARTED Jumper Installed Si
Page 23 and 24: GETTING STARTED 3.5 PPC RS232 Port
Page 25 and 26: GETTING STARTED by The Dini Group.
Page 27 and 28: GETTING STARTED 7. The AETEST Test
Page 29 and 30: INTRODUCTION TO VIRTEX-II PRO AAND
Page 45 and 46: INTRODUCTION TO THE SOFTWARE TOOLS
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INTRODUCTION TO THE SOFTWARE TOOLS
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INTRODUCTION TO THE SOFTWARE TOOLS
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PROGRAMMING/CONFIGURING THE HARDWAR
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1 BOARD HARDWARE Chapter 7 Board Ha
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BOARD HARDWARE • ~5900 Kbits of B
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BOARD HARDWARE MCU_A0 MCU_A1 MCU_A2
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BOARD HARDWARE • Receive Data TXD
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BOARD HARDWARE +3.3V +3.3V J6 1 2 3
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BOARD HARDWARE SM_CLE SM_ALE SM_WEn
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BOARD HARDWARE Table 8 - FPGA JTAG
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BOARD HARDWARE USER_BCLKp U16.AP21
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BOARD HARDWARE DDR_FCLKp U54.AT21 U
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BOARD HARDWARE Eighteen configurabl
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BOARD HARDWARE Signal Name Descript
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BOARD HARDWARE Signal Name Descript
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BOARD HARDWARE 4.3.5 Customizing th
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BOARD HARDWARE positive clock and t
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BOARD HARDWARE DDR_DCLKn U35.AU21 U
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BOARD HARDWARE Figure 29 - REFCLK/B
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BOARD HARDWARE +1.5V +2.5V +3.3V +5
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BOARD HARDWARE SRAM1_A0 SRAM1_A1 SR
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BOARD HARDWARE Figure 33 - SSRAM Pi
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BOARD HARDWARE 6.1.2 SSRAM Clocking
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BOARD HARDWARE Signal Name SRAM Pin
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BOARD HARDWARE 6.2 DDR SDRAM Double
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BOARD HARDWARE SSTL2 Class 1 termin
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BOARD HARDWARE Table 18 - Connectio
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BOARD HARDWARE Signal Name FPGA Pin
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BOARD HARDWARE The PowerPC 405 CPU
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BOARD HARDWARE Signal Name Device L
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BOARD HARDWARE power to the DN6000k
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BOARD HARDWARE Signal Name Connecto
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BOARD HARDWARE 10.2.3 Further Infor
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BOARD HARDWARE J2 +3.3V TP1 +12V +1
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BOARD HARDWARE DN6000K10PCI User Gu
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BOARD HARDWARE 12.2 DN3000K10SD Dau
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BOARD HARDWARE and the IDT74LVC1624
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BOARD HARDWARE 12.2.3 Unbuffered IO
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BOARD HARDWARE Daughter Card Connec
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BOARD HARDWARE The DN6000K10PCI PWB
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FPGA A Start End Address Read / Des
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FPGA B Start Address End Address Re
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FPGA D Start End Address Read / Des
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FPGA F Start End Address Read / Des
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Appendix B - AETEST 1 AETEST Instal
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Follow the procedures listed below
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2 AETEST Basic C++ Functions The AE
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2.3 bar_write_dword bar_write_dword
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2.5 bar_read_word bar_read_word is
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2.7 dma_buffer_allocate dma_buffer_
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2.9 dma_write_dword dma_write_dword
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2.11 pci_rdwr pci_rdwr is a functio
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2.12 DeviceIoControl DeviceIoContro
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2.12.5 Derived Functions The follow
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