User Manual

INTRODUCTION TO THE SOFTWARE TOOLS
make INCLUDE_DDR2
make EXCLUDE_DDR2
make DDR_32_MEG
make DDR_64_MEG
make DDR_128_MEG
makes changes to synplicity projects, EDK source code,
and UCF files to include DDR2
makes changes to synplicity projects, EDK source code,
and UCF files to exclude DDR2
makes changes to synplicity projects and EDK source
code to set DDR size
makes changes to synplicity projects and EDK source
code to set DDR size
makes changes to synplicity projects and EDK source
code to set DDR size
The reference design must support any number of FPGA's in both VP70 and VP100
sizes. Compiler constants are used to include/exclude code, as well as to set
appropriate parameters for the configuration being compiled for. Specifically, the user
may want to include/exclude any memory device (DDR1, DDR2, SRAM), or may
want to switch between the VP70 and VP100 part. There are four places where
changes must be made to get the desired configuration:
I. Synplicity synthesis project file
II. UCF files in 'source/ucf'
III. Xilinx EDK project file
IV. Xilinx EDK processor so urce code files ('PPC/code/fpga_params/*.h')
V. Setting up the build utility: "make.bat"
Note that the build utility runs the xilinx tools from the command line, so there are no
Xilinx Project Navigator files to edit. If you choose to use the Project Navigator GUI,
be very careful to have all the appropriate settings (ie 2vp70 vs 2vp100) The following
sections explain what to change and what options the user has to accomplish these
changes (Most are automated, some are not). It is highly recommended that everything
be recompiled after making any of these changes, including the PPC netlist, the
synplicity project, the Xilinx project, and the EDK source code. If everything is not
updated properly unpredictable behavior will result. If you aren't sure, delete all tool
generated files and start fresh. For information on the usage of the build tool
(make.bat), see the top of the ' make.bat' file.
I. SYNPLICITY SYNTHESIS PROJECT FILE
In the 'synthesis' folder there are six project files, one for each FPGA. The line
'set_option -part XC2VP70' must be modified appropriately for the VP70 or VP100.
This change, as well as changes to the parameters described below may be made
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