User Manual

GETTING STARTED
3.2 Jumper Description
Table 1 – describes the functionality of the installed jumpers on the DN6000K10PCI.
Table 1 – Jumper Description
Jumper
Installed
Signal Name
Description
JP8.A4-A3 PLL2BNC CFPGA_CLKOUT connected to RoboClock
#2 (U57). CFPGA_CLKOUT is an output
clock from the Configuration FPGA. This
connection causes 48MHz to output on all
BCLK signals, which is used in the reference
design for communication between the
Configuration FPGA and VirtexII Pro
FPGAs.
JP8.A5-B5 CLOCKB Oscillator (X8 – 33.33MHz) connected to
RoboClock #1 (U56).
JP6.A1-C1 ROBO1_REFSEL ROBOCLOCK #1, Reference Select Input:
The REFSEL input controls how the
reference input is configured. When LOW, it
will use the REFA pair (PLL1A) as the
reference input. When HIGH, it will use the
REFB pair (PLL1BC, PLL1BNC) as the
reference input. This input has an internal
pull-down.
JP6.A2-C2 ROBO1_FS ROBOCLOCK #1, Frequency Select: This
input must be set according to the nominal
frequency (fNOM). Refer to Table 1 in the
datasheet.
JP6.A4-B4 ROBO1_FBDS0 ROBOCLOCK #1, Feedback Divider
Function Select: These inputs determine the
function of the QFA0 and QFA1 outputs.
Refer to Table 4 in the datasheet.
JP6.A9-B9 ROBO1_DS0 ROBOCLOCK #1, Output Divider
Function Select: Controls the divider function
of all banks (ACLKx) of outputs. Refer to
Table 4 in the datasheet.
JP6.A10-B10 ROBO1_DS1 ROBOCLOCK #1, Output Divider
Function Select: Controls the divider function
of all banks (ACLKx) of outputs. Refer to
Table 4 in the datasheet.
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