User Manual

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GETTING STARTED 5. From the Main Menu, choose “Memory Menu”. The memory menu will now appear. 6. The DN6000k10PCI features DDR SDRAM, SRAM, and Flash memory devices. The DN6000k10PCI specific memory tests are designed to exercise and verify the functionality of those features. Select one of the memory devices to be tested. DN6000K10PCI <strong>User</strong> Guide www.dinigroup.com 16
GETTING STARTED 7. The AETEST Test utility will now test the selected memory device using the memory controllers available in the PCI reference design. Press any key to exit the selected memory device test. Congratulations! You have now programmed the DN6000k10PCI and successfully executed our AETEST utility to exercise various features of the DN6000k10PCI. 5 Playing with your DN6000k10PCI via the USB interface At this point, the DN6000k10PCI should be powered on. All present FPGAs should be programmed with the reference design bit files provided by The Dini Group. 1. Hook up the USB cable to your DN6000k10PCI and your PC. 2. When you plug in the board and start windows the first time windows should detect the board and ask for a driver. Select "install from a list" -> select "search for the best driver in these locations". Select "include the location in the search" and browse to where the INF file is located (on the product CD in “Source Code\AETEST_USB\driver\win_wdm\”) ->select "finish" 3. If the driver was installed successfully you should see the following device in the USB section of the device mananger: “DiniGroup DN6000k10PCI FLASH boot”. 4. You can now run the USB application found on the product CD in “Source Code\USBController\USBController.exe”. DN6000K10PCI <strong>User</strong> Guide www.dinigroup.com 17
Page 1 and 2: THE DINI GROUP LOGIC Emulation Sour
Page 3 and 4: Table of Contents ABOUT THIS MANUAL
Page 5 and 6: 4.6 Power PC (PPC) Clock - Sytem Cl
Page 7 and 8: 2.11.1 Description ................
Page 9 and 10: Figure 54 - Assembly drawing for th
Page 11 and 12: ABOUT THIS MANUAL Chapter 1 About T
Page 13 and 14: ABOUT THIS MANUAL Convention Meanin
Page 15 and 16: ABOUT THIS MANUAL Samir Palnitkar,
Page 17 and 18: GETTING STARTED Virtex-II Pro FPGA
Page 19 and 20: GETTING STARTED Figure 2 - Default
Page 21 and 22: GETTING STARTED Jumper Installed Si
Page 23 and 24: GETTING STARTED 3.5 PPC RS232 Port
Page 25: GETTING STARTED by The Dini Group.
Page 29 and 30: INTRODUCTION TO VIRTEX-II PRO AAND
Page 45 and 46: INTRODUCTION TO THE SOFTWARE TOOLS
Page 57 and 58: PROGRAMMING/CONFIGURING THE HARDWAR
Page 75 and 76: 1 BOARD HARDWARE Chapter 7 Board Ha
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BOARD HARDWARE • ~5900 Kbits of B
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BOARD HARDWARE MCU_A0 MCU_A1 MCU_A2
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BOARD HARDWARE • Receive Data TXD
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BOARD HARDWARE +3.3V +3.3V J6 1 2 3
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BOARD HARDWARE SM_CLE SM_ALE SM_WEn
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BOARD HARDWARE Table 8 - FPGA JTAG
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BOARD HARDWARE USER_BCLKp U16.AP21
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BOARD HARDWARE DDR_FCLKp U54.AT21 U
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BOARD HARDWARE Eighteen configurabl
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BOARD HARDWARE Signal Name Descript
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BOARD HARDWARE Signal Name Descript
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BOARD HARDWARE 4.3.5 Customizing th
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BOARD HARDWARE positive clock and t
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BOARD HARDWARE DDR_DCLKn U35.AU21 U
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BOARD HARDWARE Figure 29 - REFCLK/B
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BOARD HARDWARE +1.5V +2.5V +3.3V +5
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BOARD HARDWARE SRAM1_A0 SRAM1_A1 SR
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BOARD HARDWARE Figure 33 - SSRAM Pi
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BOARD HARDWARE 6.1.2 SSRAM Clocking
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BOARD HARDWARE Signal Name SRAM Pin
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BOARD HARDWARE 6.2 DDR SDRAM Double
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BOARD HARDWARE SSTL2 Class 1 termin
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BOARD HARDWARE Table 18 - Connectio
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BOARD HARDWARE Signal Name FPGA Pin
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BOARD HARDWARE The PowerPC 405 CPU
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BOARD HARDWARE Signal Name Device L
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BOARD HARDWARE power to the DN6000k
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BOARD HARDWARE Signal Name Connecto
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BOARD HARDWARE 10.2.3 Further Infor
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BOARD HARDWARE J2 +3.3V TP1 +12V +1
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BOARD HARDWARE DN6000K10PCI User Gu
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BOARD HARDWARE 12.2 DN3000K10SD Dau
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BOARD HARDWARE and the IDT74LVC1624
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BOARD HARDWARE 12.2.3 Unbuffered IO
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BOARD HARDWARE Daughter Card Connec
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BOARD HARDWARE The DN6000K10PCI PWB
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FPGA A Start End Address Read / Des
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FPGA B Start Address End Address Re
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FPGA D Start End Address Read / Des
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FPGA F Start End Address Read / Des
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Appendix B - AETEST 1 AETEST Instal
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Follow the procedures listed below
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2 AETEST Basic C++ Functions The AE
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2.3 bar_write_dword bar_write_dword
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2.5 bar_read_word bar_read_word is
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2.7 dma_buffer_allocate dma_buffer_
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2.9 dma_write_dword dma_write_dword
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2.11 pci_rdwr pci_rdwr is a functio
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2.12 DeviceIoControl DeviceIoContro
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2.12.5 Derived Functions The follow
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