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ABOUT THIS MANUAL 3.2 Online Document The following conventions are used in this document: Blue Text Red Text Convention Meaning or Use Example Cross-reference link to a location in the current file or in another file in the current document Cross-reference link to a location in another document See the section “Additional Resources” for details. Refer to “Title Formats” in Chapter 1 for details. See Figure 2-5 in the Virtex-II Pro Handbook Blue, underlined text Hyperlink to a website (URL) Go to http://www.xilinx.com for the latest datasheets. 4 Relevant Information Information about PCI can be obtained from the following sources: Reference the PCI Special Interest Group for the latest in PCI Express Specifications: PCI Special Interest Group http://www.pcisig.com 5440 SW Westgate Dr, #217 Portland, OR 97221, USA Phone: 503-291-2569 Fax: 503-297-1090 Other recommended specifications include: PCI Industrial Computer Manufacturers Group (PICMG) http://picmg.org 401 Edgewater Place, Suite 600 Wakefield, MA 01880, USA Phone: 781-224-1100 Fax: 781-224-1239 Suggested reference books (available from Amazon): DN6000K10PCI <strong>User</strong> Guide www.dinigroup.com 4
ABOUT THIS MANUAL Samir Palnitkar, Verilog HDL: A Guide to Digital Design and Synthesis, ISBN: 0-13- 451675-3 Sundar Rajan, Essential VHDL: RTL Synthesis Done Right Edwin Breecher, The IQ Booster: Improve Your IQ Performance Dramatically DN6000K10PCI <strong>User</strong> Guide www.dinigroup.com 5
Page 1 and 2: THE DINI GROUP LOGIC Emulation Sour
Page 3 and 4: Table of Contents ABOUT THIS MANUAL
Page 5 and 6: 4.6 Power PC (PPC) Clock - Sytem Cl
Page 7 and 8: 2.11.1 Description ................
Page 9 and 10: Figure 54 - Assembly drawing for th
Page 11 and 12: ABOUT THIS MANUAL Chapter 1 About T
Page 13: ABOUT THIS MANUAL Convention Meanin
Page 17 and 18: GETTING STARTED Virtex-II Pro FPGA
Page 19 and 20: GETTING STARTED Figure 2 - Default
Page 21 and 22: GETTING STARTED Jumper Installed Si
Page 23 and 24: GETTING STARTED 3.5 PPC RS232 Port
Page 25 and 26: GETTING STARTED by The Dini Group.
Page 27 and 28: GETTING STARTED 7. The AETEST Test
Page 29 and 30: INTRODUCTION TO VIRTEX-II PRO AAND
Page 45 and 46: INTRODUCTION TO THE SOFTWARE TOOLS
Page 57 and 58: PROGRAMMING/CONFIGURING THE HARDWAR
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PROGRAMMING/CONFIGURING THE HARDWAR
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1 BOARD HARDWARE Chapter 7 Board Ha
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BOARD HARDWARE • ~5900 Kbits of B
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BOARD HARDWARE MCU_A0 MCU_A1 MCU_A2
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BOARD HARDWARE • Receive Data TXD
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BOARD HARDWARE +3.3V +3.3V J6 1 2 3
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BOARD HARDWARE SM_CLE SM_ALE SM_WEn
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BOARD HARDWARE Table 8 - FPGA JTAG
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BOARD HARDWARE USER_BCLKp U16.AP21
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BOARD HARDWARE DDR_FCLKp U54.AT21 U
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BOARD HARDWARE Eighteen configurabl
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BOARD HARDWARE Signal Name Descript
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BOARD HARDWARE Signal Name Descript
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BOARD HARDWARE 4.3.5 Customizing th
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BOARD HARDWARE positive clock and t
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BOARD HARDWARE DDR_DCLKn U35.AU21 U
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BOARD HARDWARE Figure 29 - REFCLK/B
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BOARD HARDWARE +1.5V +2.5V +3.3V +5
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BOARD HARDWARE SRAM1_A0 SRAM1_A1 SR
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BOARD HARDWARE Figure 33 - SSRAM Pi
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BOARD HARDWARE 6.1.2 SSRAM Clocking
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BOARD HARDWARE Signal Name SRAM Pin
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BOARD HARDWARE 6.2 DDR SDRAM Double
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BOARD HARDWARE SSTL2 Class 1 termin
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BOARD HARDWARE Table 18 - Connectio
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BOARD HARDWARE Signal Name FPGA Pin
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BOARD HARDWARE The PowerPC 405 CPU
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BOARD HARDWARE Signal Name Device L
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BOARD HARDWARE power to the DN6000k
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BOARD HARDWARE Signal Name Connecto
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BOARD HARDWARE 10.2.3 Further Infor
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BOARD HARDWARE J2 +3.3V TP1 +12V +1
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BOARD HARDWARE DN6000K10PCI User Gu
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BOARD HARDWARE 12.2 DN3000K10SD Dau
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BOARD HARDWARE and the IDT74LVC1624
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BOARD HARDWARE 12.2.3 Unbuffered IO
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BOARD HARDWARE Daughter Card Connec
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BOARD HARDWARE The DN6000K10PCI PWB
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FPGA A Start End Address Read / Des
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FPGA B Start Address End Address Re
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FPGA D Start End Address Read / Des
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FPGA F Start End Address Read / Des
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Appendix B - AETEST 1 AETEST Instal
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Follow the procedures listed below
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2 AETEST Basic C++ Functions The AE
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2.3 bar_write_dword bar_write_dword
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2.5 bar_read_word bar_read_word is
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2.7 dma_buffer_allocate dma_buffer_
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2.9 dma_write_dword dma_write_dword
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2.11 pci_rdwr pci_rdwr is a functio
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2.12 DeviceIoControl DeviceIoContro
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2.12.5 Derived Functions The follow
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