User Manual

List of Figures
Figure 1 - DN6000K10PCI LOGIC Emulation Board.....................................................................................................................................................7
Figure 2 - Default Jumper Setup............................................................................................................................................................................................9
Figure 3 DN6000k10PCI Not Found.................................................................................................................................................................................20
Figure 4: Booting from FLASH...........................................................................................................................................................................................20
Figure 5: Main USBController Screen ................................................................................................................................................................................21
Figure 6 - New Project Screen Shot....................................................................................................................................................................................53
Figure 7 - Input File...............................................................................................................................................................................................................54
Figure 8: New Project Dialog Box .....................................................................................................................................................................................54
Figure 9: Project Navigator..................................................................................................................................................................................................55
Figure 10 - Main Menu..........................................................................................................................................................................................................61
Figure 11 - Interactive Configuration Option Menu........................................................................................................................................................63
Figure 12 - DN6000K10PCI Block Diagram....................................................................................................................................................................65
Figure 13 - MCU EEPROM Interface ...............................................................................................................................................................................68
Figure 14 - MCU SRAM .......................................................................................................................................................................................................69
Figure 15 - MCU FLASH .....................................................................................................................................................................................................69
Figure 16 - USB Connector ..................................................................................................................................................................................................70
Figure 17 - MCU Serial Port.................................................................................................................................................................................................70
Figure 18 – Configuration PROM/FPGA Programming Header.................................................................................................................................73
Figure 19 - SmartMedia Connector.....................................................................................................................................................................................75
Figure 20 - FPGA JTAG Connector ..................................................................................................................................................................................76
Figure 21 - Clocking Block Diagram...................................................................................................................................................................................77
Figure 22 - LVPECL Clock Input and Termination ........................................................................................................................................................82
Figure 23 - Clock Source Jumper.........................................................................................................................................................................................82
Figure 24 - RoboClock Functional Block Diagram..........................................................................................................................................................84
Figure 25 - RoboClock Configuration Jumpers ................................................................................................................................................................88
Figure 26 - External SMA Clock..........................................................................................................................................................................................90
Figure 27 - DDR DCM Implementation ...........................................................................................................................................................................92
Figure 28 - PPC External Clock...........................................................................................................................................................................................93
Figure 29 - REFCLK/BREFCLK Selection Logic ..........................................................................................................................................................95
Figure 30 - Reset Topology Block Diagram ......................................................................................................................................................................97
Figure 31 - SSRAM Connection ..........................................................................................................................................................................................99
Figure 32 - SSRAM Flow-through ....................................................................................................................................................................................100
Figure 33 - SSRAM Pipeline...............................................................................................................................................................................................101
Figure 34 - SSRAM ZBT Flow-through...........................................................................................................................................................................101
Figure 35 - SSRAM ZBT Pipeline .....................................................................................................................................................................................101
Figure 36 - Syncburst and ZBT SSRAM Timing ............................................................................................................................................................102
Figure 37 - Clock Level Translation..................................................................................................................................................................................103
Figure 38 - DDR SDRAM Connection............................................................................................................................................................................120
Figure 39 - SSTL2 Class 1 Termination............................................................................................................................................................................121
Figure 40 - SSTL2 Class 2 Termination............................................................................................................................................................................121
Figure 41 - DDR VTT Termination Regulator...............................................................................................................................................................122
Figure 42 - RocketIO Block Diagram...............................................................................................................................................................................144
Figure 43 - CPU Debug Connector ..................................................................................................................................................................................148
Figure 44 - Combined Trace/Debug Connector Pinout...............................................................................................................................................150
Figure 45 - VirtexII Pro PCI VCCO Regulator ..............................................................................................................................................................155
Figure 46 - PCI Edge Connector.......................................................................................................................................................................................156
Figure 47 - M66EN and PCIXCAP Jumper....................................................................................................................................................................162
Figure 48 - ATX Power Supply..........................................................................................................................................................................................164
Figure 49 - External Power Connection...........................................................................................................................................................................165
Figure 50 - Test Header.......................................................................................................................................................................................................168
Figure 51 - Test Header Pin Numbering..........................................................................................................................................................................168
Figure 52 - DN3000K10SD Daughter Card Block Diagram........................................................................................................................................169
Figure 53 - DN3000K10S Daughter Card .......................................................................................................................................................................170