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GETTING STARTED Jumper Installed Signal Name Description will disable to high-impedance (HI-Z). When this input is LOW, the clock outputs will disable to “HOLD-OFF” mode. When in MID, the device will enter factory test mode. 3.3 Switch Setup and Description Switch Default Position Signal Name Description S1.1 ON FPGA_MSEL0 FPGA MSEL[0] – used to set configuration mode for all VirtexII Pro FPGAs S1.2 OFF FPGA_MSEL1 FPGA MSEL[1] – used to set configuration mode for all VirtexII Pro FPGAs S1.3 OFF FPGA_MSEL2 FPGA MSEL[2] – used to set configuration mode for all VirtexII Pro FPGAs S1.4 OFF DP_SW3 Not used S3.1 ON CFPGA_MSEL0 Configuration FPGA MSEL[0] S3.2 ON CFPGA_MSEL1 Configuration FPGA MSEL[1] S3.3 ON CFPGA_MSEL2 Configuration FPGA MSEL[2] S3.4 ON Not Connected N/A 3.4 Oscillator Setup The DN6000k10PCI is shipped from the factory with a 33.33MHz in X2, 14.31818 in X3, and 100MHz in X4. If the Roboclock jumpers are set to their default locations then ACLKx will be 133.33MHz and BCLKx will be 48MHz. DN6000K10PCI <strong>User</strong> Guide www.dinigroup.com 12
GETTING STARTED 3.5 PPC RS232 Port Setup There are 4 RS232 ports that are shared with the 6 VirtexII FPGAs. These ports are multiplexed by the Configuration FPGA and can be changed via the MCU Main Menu (see Switch 4 on S2 tells MCU how to boot o If the 4th switch position is ON then the MCU boot sequence will behave in the following manner: (1) If the USB cable is plugged in when the DN6000k10 is powered-on/reset the MCU boots from the EEPROM (U8) and waits for USBController applicatin to send commands. In this case, the MCU FLASH firmware stored in U6 can be updated. In this state the MCU has limited USB functionality and cannot configure the FPGAs via USB/SmartMedia or perform many of the other USB GUI functions. (2) If the USB cable is NOT plugged in when the DN6000k10 is powered-on/reset the MCU first boots from the EEPROM (U8) and then automatically boots from the MCU FLASH (U6). In this case, the MCU FLASH can NOT be updated. o If the 4th switch position is OFF then the MCU will always boot from the MCU FLASH (U6) regardless of whether the USB cable is plugged in or not. When the MCU has booted from the FLASH it has full USB and FPGA configuration functionality. This is the default factory setup as of 1/1/05. Please note you can NOT update the MCU FLASH in the switch position. Configuring HyperTerminal). The default setup is: Port1 (P1): FPGA A Port2 (P4): FPGA F Port3 (P6): FPGA D Port4 (P7): FPGA C 3.6 Powering ON the DN6000K10PCI This section describes what is necessary to power-up the DN6000K10PCI 1. Install the SmartMedia card containing reference design into the DN6000K10PCI. 2. If switch position 4 on S1 is OFF then the MCU will automatically boot from the flash, and try to configure the FPGAs via the SmartMedia card (please see Creating Configuration File “main.txt” for information on setting up the files on the SmartMedia card). If the switch position 4 on S1 is ON then the MCU DN6000K10PCI <strong>User</strong> Guide www.dinigroup.com 13
Page 1 and 2: THE DINI GROUP LOGIC Emulation Sour
Page 3 and 4: Table of Contents ABOUT THIS MANUAL
Page 5 and 6: 4.6 Power PC (PPC) Clock - Sytem Cl
Page 7 and 8: 2.11.1 Description ................
Page 9 and 10: Figure 54 - Assembly drawing for th
Page 11 and 12: ABOUT THIS MANUAL Chapter 1 About T
Page 13 and 14: ABOUT THIS MANUAL Convention Meanin
Page 15 and 16: ABOUT THIS MANUAL Samir Palnitkar,
Page 17 and 18: GETTING STARTED Virtex-II Pro FPGA
Page 19 and 20: GETTING STARTED Figure 2 - Default
Page 21: GETTING STARTED Jumper Installed Si
Page 25 and 26: GETTING STARTED by The Dini Group.
Page 27 and 28: GETTING STARTED 7. The AETEST Test
Page 29 and 30: INTRODUCTION TO VIRTEX-II PRO AAND
Page 45 and 46: INTRODUCTION TO THE SOFTWARE TOOLS
Page 57 and 58: PROGRAMMING/CONFIGURING THE HARDWAR
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PROGRAMMING/CONFIGURING THE HARDWAR
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1 BOARD HARDWARE Chapter 7 Board Ha
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BOARD HARDWARE • ~5900 Kbits of B
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BOARD HARDWARE MCU_A0 MCU_A1 MCU_A2
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BOARD HARDWARE • Receive Data TXD
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BOARD HARDWARE +3.3V +3.3V J6 1 2 3
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BOARD HARDWARE SM_CLE SM_ALE SM_WEn
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BOARD HARDWARE Table 8 - FPGA JTAG
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BOARD HARDWARE USER_BCLKp U16.AP21
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BOARD HARDWARE DDR_FCLKp U54.AT21 U
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BOARD HARDWARE Eighteen configurabl
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BOARD HARDWARE Signal Name Descript
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BOARD HARDWARE Signal Name Descript
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BOARD HARDWARE 4.3.5 Customizing th
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BOARD HARDWARE positive clock and t
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BOARD HARDWARE DDR_DCLKn U35.AU21 U
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BOARD HARDWARE Figure 29 - REFCLK/B
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BOARD HARDWARE +1.5V +2.5V +3.3V +5
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BOARD HARDWARE SRAM1_A0 SRAM1_A1 SR
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BOARD HARDWARE Figure 33 - SSRAM Pi
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BOARD HARDWARE 6.1.2 SSRAM Clocking
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BOARD HARDWARE Signal Name SRAM Pin
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BOARD HARDWARE 6.2 DDR SDRAM Double
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BOARD HARDWARE SSTL2 Class 1 termin
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BOARD HARDWARE Table 18 - Connectio
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BOARD HARDWARE Signal Name FPGA Pin
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BOARD HARDWARE The PowerPC 405 CPU
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BOARD HARDWARE Signal Name Device L
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BOARD HARDWARE power to the DN6000k
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BOARD HARDWARE Signal Name Connecto
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BOARD HARDWARE 10.2.3 Further Infor
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BOARD HARDWARE J2 +3.3V TP1 +12V +1
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BOARD HARDWARE DN6000K10PCI User Gu
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BOARD HARDWARE 12.2 DN3000K10SD Dau
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BOARD HARDWARE and the IDT74LVC1624
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BOARD HARDWARE 12.2.3 Unbuffered IO
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BOARD HARDWARE Daughter Card Connec
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BOARD HARDWARE The DN6000K10PCI PWB
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FPGA A Start End Address Read / Des
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FPGA B Start Address End Address Re
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FPGA D Start End Address Read / Des
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FPGA F Start End Address Read / Des
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Appendix B - AETEST 1 AETEST Instal
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Follow the procedures listed below
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2 AETEST Basic C++ Functions The AE
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2.3 bar_write_dword bar_write_dword
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2.5 bar_read_word bar_read_word is
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2.7 dma_buffer_allocate dma_buffer_
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2.9 dma_write_dword dma_write_dword
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2.11 pci_rdwr pci_rdwr is a functio
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2.12 DeviceIoControl DeviceIoContro
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2.12.5 Derived Functions The follow
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