User Manual

1 EXPLORING THE REFERENCE DESIGN ....................................................................................................................................................................... 35
1.1 What is the Reference Design? ............................................................................................................................................................................. 35
1.2 Using the Reference Design.................................................................................................................................................................................. 36
1.3 Compiling the Reference Design........................................................................................................................................................................... 38
1.3.1 The Xilinx Embedded Development Kit (EDK) .......................................................................................................................................... 38
1.3.2 Synplicity Synplify........................................................................................................................................................................................ 38
1.3.3 Xilinx ISE...................................................................................................................................................................................................... 38
1.3.4 The Build Utility: Make.bat.......................................................................................................................................................................... 38
2 GETTING MORE INFORMATION ................................................................................................................................................................................. 45
2.1 Printed Documentation ......................................................................................................................................................................................... 45
2.2 Electronic Documentation .................................................................................................................................................................................... 45
2.3 Online Documentation .......................................................................................................................................................................................... 45
PROGRAMMING/CONFIGURING THE HARDWARE................................................................................................................................................. 46
1 PROGRAMMING THE CONFIGURATION FPGA ........................................................................................................................................................... 46
2 MCU DETAILS / PROGRAMMING THE MCU ............................................................................................................................................................. 50
3 CONFIGURING HYPERTERMINAL .............................................................................................................................................................................. 51
4 CONFIGURING THE FPGA USING SELECTMAP......................................................................................................................................................... 52
4.1 Bit File Generation for SelectMAP Configuration............................................................................................................................................... 53
4.2 Creating Configuration File “main.txt”............................................................................................................................................................... 57
4.2.1 Verbose Level ............................................................................................................................................................................................... 57
4.2.2 Sanity Check ................................................................................................................................................................................................. 58
4.2.3 Format of “main.txt” ..................................................................................................................................................................................... 58
4.3 Starting SelectMAP Configuration ....................................................................................................................................................................... 60
4.3.1 Description of Main Menu Options.............................................................................................................................................................. 61
4.4 Bitstream Encryption ............................................................................................................................................................................................ 64
BOARD HARDWARE ........................................................................................................................................................................................................... 65
1 INTRODUCTION TO THE BOARD................................................................................................................................................................................. 65
1.1 DN6000K10PCI Functionality ............................................................................................................................................................................. 65
2 VIRTEX-II PRO FPGA................................................................................................................................................................................................ 66
2.1 FPGA (2VP70) Facts ............................................................................................................................................................................................ 66
3 FPGA CONFIGURATION ............................................................................................................................................................................................ 67
3.1 Micro Controller Unit (MCU) .............................................................................................................................................................................. 67
3.1.1 MCU EEPROM Interface ............................................................................................................................................................................. 68
3.1.2 MCU SRAM External................................................................................................................................................................................... 68
3.1.3 MCU FLASH ................................................................................................................................................................................................ 69
3.1.4 MCU USB 2.0 Interface................................................................................................................................................................................ 69
3.1.5 RS232 Interface............................................................................................................................................................................................. 70
3.2 Configuration FPGA............................................................................................................................................................................................. 71
3.2.1 Configuration PROM/FPGA Programming ................................................................................................................................................. 72
3.2.2 Design Notes on the Configuration FPGA ................................................................................................................................................... 73
3.3 SmartMedia ........................................................................................................................................................................................................... 74
3.3.1 SmartMedia Connector ................................................................................................................................................................................. 74
3.3.2 SmartMedia connection to Spartan (Configuration FPGA)/MCU............................................................................................................... 75
3.4 Boundary-Scan (JTAG, IEEE 1532) Mode........................................................................................................................................................... 76
3.4.1 FPGA JTAG Connector ................................................................................................................................................................................ 76
3.4.2 FPGA JTAG connection to Configuration FPGA........................................................................................................................................ 76
4 CLOCK GENERATION ................................................................................................................................................................................................. 77
4.1 Clock Methodology ............................................................................................................................................................................................... 77
4.2 Clock Source Jumpers........................................................................................................................................................................................... 81
4.2.1 Clock Source Jumper Header........................................................................................................................................................................ 82
4.3 Roboclocks ............................................................................................................................................................................................................ 82
4.3.1 RoboClock PLL Clock Buffers..................................................................................................................................................................... 82
4.3.2 RoboClock Configuration Jumpers............................................................................................................................................................... 84
4.3.3 Roboclock Configuration Headers................................................................................................................................................................ 88
4.3.4 Useful Notes and Hints ................................................................................................................................................................................. 88
4.3.5 Customizing the Oscillators.......................................................................................................................................................................... 89
4.3.6 Common Clock Source Selections................................................................................................................................................................ 89
4.4 External Clocks ..................................................................................................................................................................................................... 89
4.4.1 External SMA Clock..................................................................................................................................................................................... 90
4.4.2 Connections between FPGA’s and External SMA Clock Buffer................................................................................................................. 90
4.5 DDR Clocking ....................................................................................................................................................................................................... 90
4.5.1 Clocking Methodology ................................................................................................................................................................................. 91
4.5.2 Connections between FPGA’s and DDR PLL Clock Buffer ....................................................................................................................... 92