Hardware Interface Description - Wireless Data Modules

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MC55/56 Hardware Interface Description Confidential / Released s 3.3.1.1 Turn on MC55/56 using the ignition line /IGT (Power on) To switch on MC55/56 the /IGT (Ignition) signal needs to be driven to ground level for at least 100ms and not earlier than 10ms after the last falling edge of VDD. This can be accomplished using an open drain/collector driver in order to avoid current flowing into this pin. BATT+ min. 10ms HiZ min. 100ms HiZ /IGT VDD ca. 60ms /TXD0 /TXD1 /DSR0 /EMERGOFF Software controlled Serial interfaces ASC0 and ASC1 Undefined Inactive Active ca. 300ms ca. 900ms For details please see Chapter 3.3.1.2 Figure 3: Power-on by ignition signal If configured to a fix baud rate, MC55/56 will send the result code ^SYSSTART to indicate that it is ready to operate. This result code does not appear when autobauding is active. See Chapter AT+IPR in [1]. In a battery operated MC55/56 application, the duration of the /IGT signal must be 1s minimum when the charger is connected and you may want to go from Charge only mode to Normal mode. MC55/56_hd_v02.06 Page 28 of 105 29.10.2004
MC55/56 Hardware Interface Description Confidential / Released s 3.3.1.2 Timing of the ignition process When designing your application platform take into account that powering up MC55/56 requires the following steps. • The ignition line cannot be operated until V BATT+ passes the level of 3.0V. • The ignition line shall not be operated earlier than 10ms after the last falling edge of VDD. • 10ms after V BATT+ has reached 3.0V the ignition line can be switched low. The duration of the falling edge must not exceed 1ms. • Another 100ms are required to power up the module. • Ensure that V BATT+ does not fall below 3.0V while the ignition line is driven. Otherwise the module cannot be activated. • If the VDDLP line is fed from an external power supply as explained in Chapter 3.8, the /IGT line is HiZ before the rising edge of BATT+. 3.0V BATT+ 0V HiZ HiZ /IGT 10ms max. 1ms min. 100ms Figure 4: Timing of power-on process if VDDLP is not used 3.0V BATT+ /IGT 0V HiZ HiZ 10ms max. 1ms min. 100ms Figure 5: Timing of power-on process if VDDLP is fed from external source MC55/56_hd_v02.06 Page 29 of 105 29.10.2004
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