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Point Grey <strong>Blackfly</strong> Technical Reference<br />
Appendix C: Control and Status Registers<br />
C.4 GPIO_CTRL_PIN: 1110h-1140h<br />
These registers provide control over the GPIO pins.<br />
Pin Register<br />
0 GPIO_CTRL_PIN_0 1110h<br />
1 GPIO_CTRL_PIN_1 1120h<br />
Format:<br />
Field Bit Description<br />
Presence_Inq [0]<br />
Pin_Mode [12-15]<br />
[1-11] Reserved<br />
[16-30]<br />
Data [31]<br />
Presence of this feature<br />
0: Not Available, 1: Available<br />
Current GPIO Mode:<br />
0: Input<br />
1: Output<br />
2: Asynchronous Trigger<br />
3: Strobe<br />
4: Pulse width modulation (PWM)<br />
For Modes 0, 1, and 2: Reserved<br />
For Mode 4 (PWM:) see below<br />
For Modes 0, 1, and 2: Data field<br />
0 = 0 V (falling edge), 1 = +3.3 V (rising edge)<br />
For Mode 4 (PWM): see below<br />
Number of PWM pulses<br />
Pwm_Count [16-23]<br />
Read: The current count; counts down the remaining pulses. After reaching zero, the count<br />
does not automatically reset to the previously-written value.<br />
En_Pin [25-27]<br />
Disable_Pol [29]<br />
En_En [30]<br />
Pwm_Pol [31]<br />
[24] Reserved<br />
[28] Reserved<br />
Write: Writing the number of pulses starts the PWM. Write 0xFF for infinite pulses. (Requires<br />
write of 0x00 before writing a different value.)<br />
The GPIO pin to be used as a PWM enable i.e. the PWM continues as long as the En_Pin is<br />
held in a certain state (high or low).<br />
Polarity of the PWM enable pin (En_Pin) that will disable the PWM. If this bit is 0, the PWM is<br />
disabled when the PWM enable pin goes low.<br />
0: Disable enable pin (En_Pin) functionality<br />
1: Enable En_Pin functionality<br />
Polarity of the PWM signal<br />
0: Low, 1: High<br />
Revised 12/13/2012<br />
Copyright ©2012 Point Grey Research Inc.<br />
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