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MITSUBISHI MICROCOMPUTERSMELPS 8-41 SLAVE MICROCOMPUTERSFUNCTIONS OF MELPS 8-41 SLAVE MICROCOMPUTERSThe individual terminals of the quasi-bidirectional portscan be used for input or output. Some terminals, therefore,can be in the input mode while the remaining terminalsof a port are in the output mode. This capabilityof ports 1 and 2 is convenient for inputting or outputting1-bit data with few bits. The logical instructions ANLand ORL can easily be used to manipulate the input oroutput of these ports.(2) Data busThe data bus (00 0 """ 00 7 ) handles the data, commandsand statuses between the master CPU and MELPS 8-41. It is controlled by the following 4 control signals.Table 2 shows the relationship between the control signalsand the data bus.Ao : Address input indicating data/command busbuffer registers and status registerR : Read inputW : Write inputS : Chip select inputDQo-DQ7 .:..SoAoAo,}SoWSoAoAjj8/I'StatusST7 MOV STS,AST6 4STsST4FlFaIBFOBFInternalbusOutput data OUT DBB, Abus buffer 8-/(OBB(O»~Table 2Control signals and data busS R W Ao Data bus mode Data on data bus0 0 1 0 Read Data0 0 1 1 Read Status0 1 0 0 Write Data0 1 0 1 Write Command (F, .... 1 )1 X X X High impedance -SoW8,'"InputIN A, OBBdata/command8bus buffer ~(08B(I»IIThe internal configuration of the data bus is shown in Fig. 7.The functions of the 3 registers indicated (status register,output data bus buffer register and input data/commandbus buffer register) are now described in detail.Flg.6Internal configuration of data bus controlFlg.7Internal configuration of data bus• Status registerThe status register is c9nfigured with 8 bits and the highorder4 bits (ST 4 -ST 7 1 can be set as required with a software(MOV STS, A) instructions. The low-order 4 bits (OBF,IBF, Fo, F 1 ) are set as follows:OBF (output buffer full)The OBF flag is automatically set to "1" when the output instruction(OUT DBB, A) is executed inside the MELPS 8-41and it is cleared when the contents of the output data busbuffer are read by the master CPU.IBF (input buffer full)The IBF flag is automatically set to "1" when the data orcommands are written into the input data/command busbuffer by the master CPU and it is cleared when the inputinstruction (IN A, DBB) is executed inside the MELPS 8-41.Fo (flag 0)The Fo flag is set by the flag setting instructions (CPL Fo,CLR Fo) and it is used to inform the master CPU of the internalstate of the MELPS 8-41.• MITSUBISHI"'ELECTRIC5-7
MITSUBISHI MICROCOMPUTERSMELPS8·41 SLAVE MICROCOMPUTERSFUNCTIONS OF MELPS 8·41 SLAVE MICROCOMPUTERSF1 (flag 1)When the data or command is input into the input datalcommand bus buffer by the master CPU, the F1 flag is setto the condition of the Ao input.The F1 flag is also set by the flag setting instructions (CPLF1, CLR F1).• Output Data Bus Buffer RegisterThe accumulator (A) contents are transferred to the DBB(0) output data bus buffer register by the OUT DBB, A instruction.Since the OBF flag is set at this time, the masterCPU can judge whether the data has been transferred tothe register by confirming the state of the OBF flag.• Input Data/Command Bus Buffer (DBB(l)) RegisterWhen the write request (W =0) is generated from the masterCPU, the data on the data bus is transferred to the DBB(1) input data/command bus buffer register. Since the IBFflag is set at this time, it is possible to judge whether thedata or command has been transferred inside the MELPS8-41 by confirming the state Qf this flag.Conditional Jumps Using Pins To, T1and Flags IBF, OBFThe conditional jump instructions are used to alter· programs,depending on the internal and external conditions(states) of the CPU. Details of the jump instructions can befound in the section on machine instructions.The input signal status of pins To and T1, and the states ofthe IBF and OBF flags can be checked by the conditionaljump instructions. These input pins, through conditionaljump instructions such as JTO and JNTO, can be used tocontrol a program. This means that programs and processingtime can be reduced by being able to test data i':l theinput pin rather than reading the data into a accumulatorand then testing it.Pin T1 has other functions and uses which are not related toconditional jump instructions. Details of these other functionsand uses can be f.ound on the section dealing with pinfunctions.The unconditional jump instructions for enabling a jump tobe made to the address where the ordinary interrupt pro,cessing program is stored are contained in address 3 of theprogram memory.The interrupt level is one so that the next interrupt cannotbe accepted until the current interrupt processing has beencompleted. The RETR instruction terminates the interruptprocessing. That is to say, the next interrupt cannot beaccepted until the RETR instruction is executed. The nextinterrupt can be accepted at the start of the second cycleof the RETR instruction (2-cycle instruction). Timer/eventcounter overflow which causes an interrupt request will alsonot be accepted.Priority is given to the external interrupt when both an externalinterrupt and timer interrupt have been generated atthe same time.CDTIMER INTERRUPT ENABLE FF (TCNTF)®TlMER INTERRUPT REQUEST FF (TIRF)@EXTERNAL INTERRUPT LATCH@EXTERNAL INTERRUPT ENABLE FF (INTF)@INTERRUPT ENABLE FF (IEF)@INTERRUPT ACKNOWLEDGE FFQ)EXTERNAL INTERRUPT PENDING FF (EIPF)InterruptThe CPU reco~nizes ~n external interrupt by a low-levelsignal at the Sand W pins. When such an interrupt isaccepted, the external interrupt pending flip-flop and IBFflag are set.Interrupt requests are sampled between the SYNC signaloutputs of every machine cycle. When a request is recognized,then as soon as the instruction being executed isterminated, a subroutine call is made to address 3 of theprogram memory. As with ordinary subroutine calls, theprogram counter and program status word (PSW) are savedin the program counter stack.Flg.SInterrupt control section configuration5-8 •. MITSUBISHI.... ELECTRIC
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MITSUBISHI MICROCOMPUTERSCONTENTSDG
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GUIDANCE D
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MITSUBISHI MICROCOMPUTERSDEVELOPMEN
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MITSUBISHI MICROCOMPUTERSORDERING I
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MITSUBISHI MICROCOMPUTERSLE,:lTER S
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MITSUBISHI MICROCOMPUTERSSYMBOLOGYN
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. MITSUBISHI MICROCO.MPUTERSQUALITY
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MITSUBISHI MICROCOMPUTERSPRECAUTION
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MITSUBISHI MICROCOMPUTERSMS0760·XX
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60 16 12 16 A0 16 AOC $A012Absolute
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MIC-ROCOMPUTER SUPPORT SYSTEMS
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APPENDICES
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CONTACT ADDRESSES FOR FURTHER INFOR
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1984 MITSUBISHI DATA BOOKSINGLE-CHI
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MEMO
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