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MITSUBISHI MICROCOMPUTERSMELPS 8-41 SLAVE MICROCOMPUTERSFUNCTIONS OF MELPS 8-41 SLAVE MICROCOMPUTERSTable 3 Acceptance of InterruptsItem Conditions Execution detailsInternal Interrupt When TCNTEF No external interrupt Interrupt is executed and call is mode to address 7.(timer INT enable FF) = 1 I During external interrupt executionInterrupt is held.When TCNTFInterrupt is not executed or held.(timer INT enable FF ) = 0 TF (Timer flag)+- 1External interrupt When INo timer interrupt Interrupt is executed and call is made to address 3.(external INT enable FF) = 1 I During timer Interrupt execution IWhen (external INT enable FF) = 0Timer and external interruptsCombination is same as conditions abovegenerated simultaneouslyInterrupt is not executed but held.External interrupt takes priority and is executed.When a second level of external interrupt is' required, thetimer interrupt, if not being used, can provide this. This isdone by enabling the timer/event counter interrupt and settingthe timer/event counter to FF 16 • The CPU is placed inthe event counter mode. The interrupt is then generated inaddress 7 by setting the Tl input from the external sourcefrom the high to low level.The IBF flag can be tested using a conditional. jump instruction.For further details, check the section on the conditionaljump instructions, pins To and Tlo and the IBF andOBF flags.Timer I Event CounterThe timer/event counter for the MELPS 8-41 is an 8-bitcounter, that is used to measure time delays or count externalevents but not both. The same counter is used to measuretime delays or count external events simply by changingthe input to the counter.The counter can be initialized by executing an MOV T, Ainstruction. The value of the counter can be read for checkingby executing the MOV A, T instruction. Reset will stopthe counting but the counter is not cleared, thus enablingcounting to be resumed.The largest number the counter can contain is FF 16 . If it isincremented by 1 when it contains FF 16 , the counter will bereset to 00 16 , the overflow flag is set and a timer interruptrequest is issued. The timer flag can be checked using theJTF conditional branch instruction, and it is cleared by executingthe JTF instruction or by resetting the system.When the timer interrupt is accepted, a subroutine call i!rmade to address 7 of the program memory.When both a timer and external interrupt request aregenerated at the same time, the external interrupt is givenpriority and will be accepted first by automatically calling toaddress 3 of the program memory. The timer interrupt requestis kept and will be processed when the external interrupthas been completed and a RETR instruction is executed.A latched timer interrupt request is cancelled whena timer interrupt request is generated. The STRT CNT instructionis used to change the counter to an event counter.Then the pin Tl signal becomes the input to the eventcounter and events are counted up at the Tl fall. The maximumrate that can be counted is one time in 3 machine cycles(7.5J.Ls when using a 6MHz crystal). The high-level atTl must be maintained at least * of the cycle time (500nswith a 6MHi: crystal).The STRT T instruction is used to change the counter to atimer. The internal clock signal becomes the input to thetimer. The internal clock is 3~ of 400kHz (with a 6MHzcrystal) or 12.5kHz (see Fig. 9). The timer is thereforecounted up every 80J.Ls. The counter can be initialized byexecuting an MOV T, A instruction. Delay times varyingfrom 80J.Ls to 20ms (256 count) can be obtained by detectingthe counter overflows. Even times of more than 20ms canbe achieved by counting the number of overflows using theprogram.A resolution of less than 80J.Ls can be obtained in the eventcounter mode by supplying an external clock to pin T 1 . It isalso possible to supply every third (or more) prescaled ALEsignal to pin Tl instead of an external clock.II• MITSUBISHI.... ELECTRIC5;""9
MITSUBISHI MICROCOMPUTERSMELPS 8-41 SLAVE MICROCOMPUTERSFUNC.TIONS OF MELPS 8-41 SLAVE MICROCOMPUTERSTIMEROVERFLOW2.5tis·(when using a6MHz crystal)Instruciton cycleI 85 Sl 82 83 T S4 I 85 81 IInstructionInstruction programdecode,Instruction executionfetch counterrenewalTIMERFLAG (TF)S 0Flg.12Instruction execution timingFlg.9EOGE OE TECTORTimer/event counter configurationCycle TimingThe output of the state counter is + the input frequencyfrom the oscillator, and a ClK signal is produced which determinesthe times of each machine state (see Fig. 10) .During the cycle count the ClK signal is prescaled by +and a machine cycle containing 5 states is produced. TheMElPS 8-41 instructions are executed in one or twomachine cycles. Fig. 12 shows the internal operation with aninstruction for~ed from one machine cycle.ResetThe RESET pin is for resetting the CPU. A Schmitt triggercircuit along with a pull-up resistor are connected to it onthe chip. A sufficiently long pulse can be obtained for resettingby attaching 1 J..l F capacitor as shown in Fig. 13. Anexternal reset pulse applied at RESET must remain at thelow level for at least 10ms after the power has been turnedon and after it has reached its normal level.The reset function causes the following initialization withinthe CPU.(1) The program counter is reset to O.(2) The stack pointer is reset to O.(3) The register bank 0 is selected.(4) Ports 1 and 2 are reset to the input mode.(5) External and timer interrupts are reset to disable state.(6) Timer is stopped.(7) Timer flag is cleared.(8) Flags Fo and F1 are cleared.MELPS8-41Flg.l0 Clock generator circuit5VInternalclock~.~~l- "SYNC -4--+-__ ~Flg.13Example of reset circuitPROGt--r--1--rIL~_~-4_~Flg.llClock and generated cycle signals5-10 • MITSUBISHI"'ELECTRIC
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MITSUBISHI MICROCOMPUTERSCONTENTSDG
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GUIDANCE D
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MITSUBISHI MICROCOMPUTERSDEVELOPMEN
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MIC-ROCOMPUTER SUPPORT SYSTEMS
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APPENDICES
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CONTACT ADDRESSES FOR FURTHER INFOR
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1984 MITSUBISHI DATA BOOKSINGLE-CHI
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