Formal Verification with Yosys-SMTBMC Clifford Wolf

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assert(), assume(), restrict() ● assert(expression) – Error if the expression evaluates to false ● assume(expression) – Simulation: Error if expression evaluates to false – Verification: Only consider traces where expression is true ● restrict(expression) – Simulation: Ignored. – Verification: Only consider traces where expression is true ● When to use assume(), when restrict()? – Use assume() if your asserts depend on it, use restrict() when it's just there to help with the proof, but the asserts would hold without it.
Immediate assertions, Concurrent assertions ● Immediate assertions: assert(), assume(), or restrict() within an always or initial block, with an expression as argument. This is fully supported by Yosys. For example: – initial assume (foo < bar); – always @* assert (2*foo > bar); – always @(posedge clk) if (foo < 10) restrict(bar > 10); ● Concurrent assertions: Asserting a SystemVerilog property in module context. So far Yosys only supports simple expression properties: – assert property (expression); is identical to: – always @* assert(expression);
Page 1 and 2: Formal Verification with Yosys-SMTB
Page 3 and 4: Availability of various EDA tools f
Page 5 and 6: Why Formal Verification? ● Prove
Page 7 and 8: Yosys-SMTBMC Examples ● Slides an
Page 9: Hello World yosyssmtbmc hello1.sm
Page 13 and 14: Hello Test-Bench module hello(input
Page 15 and 16: Bounded vs. Unbounded Methods ●
Page 17 and 18: Temporal Induction Assuming we have
Page 19 and 20: SAT Solving and SMT Solving ● Sat
Page 21 and 22: Yosys-SMTBMC Flow Verilog Design Ve
Page 23 and 24: eachable states assertions
Page 25 and 26: demo1.v
Page 27 and 28: demo2.v $ make demo2 yosyssmtbmc
Page 29 and 30: memcmp.v module memory1 ( input clk
Page 31 and 32: memcmp.v module memcmp ( input clk,
Page 33 and 34: axicheck.v // only deassert “vali
Page 35 and 36: Bounded Liveness Properties ● Saf
Page 37 and 38: multiclk.v module multiclk(input cl
Page 39 and 40: setreset.v module setreset(input cl
Page 41 and 42: abccex.v module abccex(input clk, i
Page 43 and 44: Benchmark ● See benchmark.zip and
Page 45 and 46: Benchmark
Page 47 and 48: Benchmark
Page 49 and 50: Custom Flows Verilog Design Yosys V
Page 51 and 52: cycle3.tpl (setlogic QF_UFBV) ; i
Page 53 and 54: cycle3.tpl $ yosys ql cycle3.yslo
Page 55 and 56: Future Work ● Limited support for

Formal Verification with Yosys-SMTBMC Clifford Wolf

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