Formal Verification with Yosys-SMTBMC Clifford Wolf

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memcmp.v module memory2 ( input clk, input [3:0] wstrb, input [15:0] waddr, input [15:0] raddr, input [31:0] wdata, output [31:0] rdata ); reg [31:0] mem [0:2**161]; reg [31:0] buffered_wdata; reg [31:0] buffered_rdata; reg [3:0] buffered_wstrb; reg waddr_is_not_raddr; wire [31:0] expanded_wstrb = {{8{wstrb[3]}}, {8{wstrb[2]}}, {8{wstrb[1]}}, {8{wstrb[0]}}}; wire [31:0] expanded_buffered_wstrb = {{8{buffered_wstrb[3]}}, {8{buffered_wstrb[2]}}, {8{buffered_wstrb[1]}}, {8{buffered_wstrb[0]}}}; assign rdata = waddr_is_not_raddr ? buffered_rdata : (buffered_wdata & expanded_buffered_wstrb) | (buffered_rdata & ~expanded_buffered_wstrb); always @(posedge clk) begin mem[waddr]
memcmp.v module memcmp ( input clk, input [3:0] wstrb, input [15:0] waddr, input [15:0] raddr, input [31:0] wdata, output [31:0] rdata1, output [31:0] rdata2 ); memory1 mem1 ( .clk (clk ), .wstrb(wstrb ), .waddr(waddr ), .raddr(raddr ), .wdata(wdata ), .rdata(rdata1) ); memory2 mem2 ( .clk (clk ), .wstrb(wstrb ), .waddr(waddr ), .raddr(raddr ), .wdata(wdata ), .rdata(rdata2) ); endmodule memcmp.smtc initial assume (= [mem1.mem] [mem2.mem]) always 1 assert (= [mem1.mem] [mem2.mem]) assert (= [rdata1] [rdata2]) $ yosyssmtbmc t 5 smtc memcmp.smtc memcmp.smt2 ## 0 0:00:00 Solver: z3 ## 0 0:00:00 Checking asserts in step 0.. ## 0 0:00:00 Checking asserts in step 1.. ## 0 0:00:00 Checking asserts in step 2.. ## 0 0:00:00 Checking asserts in step 3.. ## 0 0:00:00 Checking asserts in step 4.. ## 0 0:00:00 Status: PASSED $ yosyssmtbmc t 5 smtc memcmp.smtc i memcmp.smt2 ## 0 0:00:00 Solver: z3 ## 0 0:00:00 Trying induction in step 5.. ## 0 0:00:00 Trying induction in step 4.. ## 0 0:00:00 Temporal induction successful. ## 0 0:00:00 Status: PASSED
Page 1 and 2: Formal Verification with Yosys-SMTB
Page 3 and 4: Availability of various EDA tools f
Page 5 and 6: Why Formal Verification? ● Prove
Page 7 and 8: Yosys-SMTBMC Examples ● Slides an
Page 9 and 10: Hello World yosyssmtbmc hello1.sm
Page 11 and 12: Immediate assertions, Concurrent as
Page 13 and 14: Hello Test-Bench module hello(input
Page 15 and 16: Bounded vs. Unbounded Methods ●
Page 17 and 18: Temporal Induction Assuming we have
Page 19 and 20: SAT Solving and SMT Solving ● Sat
Page 21 and 22: Yosys-SMTBMC Flow Verilog Design Ve
Page 23 and 24: eachable states assertions
Page 25 and 26: demo1.v
Page 27 and 28: demo2.v $ make demo2 yosyssmtbmc
Page 29: memcmp.v module memory1 ( input clk
Page 33 and 34: axicheck.v // only deassert “vali
Page 35 and 36: Bounded Liveness Properties ● Saf
Page 37 and 38: multiclk.v module multiclk(input cl
Page 39 and 40: setreset.v module setreset(input cl
Page 41 and 42: abccex.v module abccex(input clk, i
Page 43 and 44: Benchmark ● See benchmark.zip and
Page 45 and 46: Benchmark
Page 47 and 48: Benchmark
Page 49 and 50: Custom Flows Verilog Design Yosys V
Page 51 and 52: cycle3.tpl (setlogic QF_UFBV) ; i
Page 53 and 54: cycle3.tpl $ yosys ql cycle3.yslo
Page 55 and 56: Future Work ● Limited support for

Formal Verification with Yosys-SMTBMC Clifford Wolf

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