Formal Verification with Yosys-SMTBMC Clifford Wolf

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Yosys Flows ● Synthesis ● Formal Verification – iCE40 FPGAs – Yosys-STMBMC (Project IceStorm) ● ● Bounded Model Checking Using any SMT-LIB2 solver – Xilinx 7-Series FPGAs (Vivado for place&route) ● (using QF_AUFBV logic) Supported solvers: Z3, CVC4, Yices, ... – ASIC Flows – Yosys built-ins ● ● ● Qflow Coriolis2 Efabless.com Open Galaxy ● ● SAT solver Equiv checking framework – Yosys + ABC – Custom flows ● From simple toy projects ● Synthesis + miter generation in Yosys, write BLIF, solve in ABC to PhD studies
Availability of various EDA tools for students, hobbyists, enthusiasts ● ● FPGA Synthesis – Free to use: ● Formal Verification – Free to use: ● Xilinx Vivado WebPack, etc. ● ??? ● Yosys + Project IceStorm ● VTR (Odin II + VPR) ● ??? * ● Xilinx XSIM, etc. – Free and Open Source: HDL Simulation – Free to use: – Free and Open Source: – Free and Open Source: .. and people in the industry are complaining they can't find any verification experts to hire! * There are a few contenders, but they lack complete Verilog frontends, thus can't really be used with existing Verilog designs.
Page 1: Formal Verification with Yosys-SMTB
Page 5 and 6: Why Formal Verification? ● Prove
Page 7 and 8: Yosys-SMTBMC Examples ● Slides an
Page 9 and 10: Hello World yosyssmtbmc hello1.sm
Page 11 and 12: Immediate assertions, Concurrent as
Page 13 and 14: Hello Test-Bench module hello(input
Page 15 and 16: Bounded vs. Unbounded Methods ●
Page 17 and 18: Temporal Induction Assuming we have
Page 19 and 20: SAT Solving and SMT Solving ● Sat
Page 21 and 22: Yosys-SMTBMC Flow Verilog Design Ve
Page 23 and 24: eachable states assertions
Page 25 and 26: demo1.v
Page 27 and 28: demo2.v $ make demo2 yosyssmtbmc
Page 29 and 30: memcmp.v module memory1 ( input clk
Page 31 and 32: memcmp.v module memcmp ( input clk,
Page 33 and 34: axicheck.v // only deassert “vali
Page 35 and 36: Bounded Liveness Properties ● Saf
Page 37 and 38: multiclk.v module multiclk(input cl
Page 39 and 40: setreset.v module setreset(input cl
Page 41 and 42: abccex.v module abccex(input clk, i
Page 43 and 44: Benchmark ● See benchmark.zip and
Page 45 and 46: Benchmark
Page 47 and 48: Benchmark
Page 49 and 50: Custom Flows Verilog Design Yosys V
Page 51 and 52: cycle3.tpl (setlogic QF_UFBV) ; i
Page 53 and 54:
cycle3.tpl $ yosys ql cycle3.yslo
Page 55 and 56:
Future Work ● Limited support for
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Formal Verification with Yosys-SMTBMC Clifford Wolf

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