Formal Verification with Yosys-SMTBMC Clifford Wolf

Immediate assertions,
Concurrent assertions
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Immediate assertions: assert(), assume(), or restrict()
within an always or initial block, with an expression as
argument. This is fully supported by Yosys. For example:
– initial assume (foo < bar);
– always @* assert (2*foo > bar);
– always @(posedge clk) if (foo < 10) restrict(bar > 10);
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Concurrent assertions: Asserting a SystemVerilog property in
module context. So far Yosys only supports simple expression
properties:
– assert property (expression);
is identical to:
– always @* assert(expression);