Formal Verification with Yosys-SMTBMC Clifford Wolf

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PicoRV32 AXI Check ● The AXIS (AXI Stream) Interface: – axis_ready (1 bit, slave → master) – axis_valid (1 bit, master → slave) – axis_data (N bits, master → slave) – Data is transferred when axis_valid and axis_ready are both active in the same cycle. ● The example checks an AXI4-Lite interface (picorv32_axi), which consists of 5 individual AXI Streams. ● Properties to check: – Easy (axicheck.v * ): ● ● ● axis_valid must only be deasserted directly after a successful transfer axis_ready must only be deasserted directly after a successful transfer axis_data must be stable while axis_valid is asserted – Hard (axicheck2.v * ): ● axis_valid being asserted must not depend on axis_ready also being asserted * https://github.com/cliffordwolf/picorv32/tree/master/scripts/smtbmc/
axicheck.v // only deassert “valid” after successful transfer if ($fell(mem_axi_awvalid)) begin assert($past(mem_axi_awready)); end // only deassert “ready” after successful transfer if ($fell(mem_axi_awready)) begin assume($past(mem_axi_awvalid)); end // data must be stable while “valid” is active if ($past(mem_axi_awvalid && !mem_axi_awready)) begin assert($stable(mem_axi_awaddr)); assert($stable(mem_axi_awprot)); end 5x for the 5 AXI Streams, swapping assume() and assert() for slave interfaces + some additional checks to make sure the traffic on the 5 streams is consistent. E.g. no read results are received <strong>with</strong>out a read request first being sent.
Page 1 and 2: Formal Verification with Yosys-SMTB
Page 3 and 4: Availability of various EDA tools f
Page 5 and 6: Why Formal Verification? ● Prove
Page 7 and 8: Yosys-SMTBMC Examples ● Slides an
Page 9 and 10: Hello World yosyssmtbmc hello1.sm
Page 11 and 12: Immediate assertions, Concurrent as
Page 13 and 14: Hello Test-Bench module hello(input
Page 15 and 16: Bounded vs. Unbounded Methods ●
Page 17 and 18: Temporal Induction Assuming we have
Page 19 and 20: SAT Solving and SMT Solving ● Sat
Page 21 and 22: Yosys-SMTBMC Flow Verilog Design Ve
Page 23 and 24: eachable states assertions
Page 25 and 26: demo1.v
Page 27 and 28: demo2.v $ make demo2 yosyssmtbmc
Page 29 and 30: memcmp.v module memory1 ( input clk
Page 31: memcmp.v module memcmp ( input clk,
Page 35 and 36: Bounded Liveness Properties ● Saf
Page 37 and 38: multiclk.v module multiclk(input cl
Page 39 and 40: setreset.v module setreset(input cl
Page 41 and 42: abccex.v module abccex(input clk, i
Page 43 and 44: Benchmark ● See benchmark.zip and
Page 45 and 46: Benchmark
Page 47 and 48: Benchmark
Page 49 and 50: Custom Flows Verilog Design Yosys V
Page 51 and 52: cycle3.tpl (setlogic QF_UFBV) ; i
Page 53 and 54: cycle3.tpl $ yosys ql cycle3.yslo
Page 55 and 56: Future Work ● Limited support for

Formal Verification with Yosys-SMTBMC Clifford Wolf

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