Formal Verification with Yosys-SMTBMC Clifford Wolf

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End-to-end Formal Verification of RISC-V Cores with riscvformal ● ● ● ● riscvformal is a framework for formal verification of RISC-V Processor Cores, using Yosys-SMTBMC and ither Yosys-based verification flows. A separate verification task for each instruction And a few additional verification tasks to verify consistent state between instructions and correct implementation of memory I/O Project is in its early stages and under construction! Only RV32I support at the moment. https://github.com/cliffordwolf/riscv-formal
Future Work ● Limited support for SVA properties – Using AST transformations to clocked always blocks with immediate assertions. – However: I highly recommend sticking to immediate assertions in new code. It does not look like FOSS simulators are going to support SVA properties anytime soon. ● Improved support for Verilog x-propagation – Currently only available with Yosys “sat” flow – Using a Yosys pass that adds transforms into a circuit problem without x-progatation (using explicit *__x nets) ● Yosys C Back-End – There exist a few FOSS formal verification tools for C (e.g. ESBMC) – A C back-end would enable verification flows that check against formal specs written in C. ● SymbiYosys – A front-end driver for Yosys-SMTBMC and other Yosys-based verification flows – “Push-button solution” for a wide range of HDL verification tasks.
Page 1 and 2:
Formal Verification with Yosys-SMTB
Page 3 and 4: Availability of various EDA tools f
Page 5 and 6: Why Formal Verification? ● Prove
Page 7 and 8: Yosys-SMTBMC Examples ● Slides an
Page 9 and 10: Hello World yosyssmtbmc hello1.sm
Page 11 and 12: Immediate assertions, Concurrent as
Page 13 and 14: Hello Test-Bench module hello(input
Page 15 and 16: Bounded vs. Unbounded Methods ●
Page 17 and 18: Temporal Induction Assuming we have
Page 19 and 20: SAT Solving and SMT Solving ● Sat
Page 21 and 22: Yosys-SMTBMC Flow Verilog Design Ve
Page 23 and 24: eachable states assertions
Page 25 and 26: demo1.v
Page 27 and 28: demo2.v $ make demo2 yosyssmtbmc
Page 29 and 30: memcmp.v module memory1 ( input clk
Page 31 and 32: memcmp.v module memcmp ( input clk,
Page 33 and 34: axicheck.v // only deassert “vali
Page 35 and 36: Bounded Liveness Properties ● Saf
Page 37 and 38: multiclk.v module multiclk(input cl
Page 39 and 40: setreset.v module setreset(input cl
Page 41 and 42: abccex.v module abccex(input clk, i
Page 43 and 44: Benchmark ● See benchmark.zip and
Page 45 and 46: Benchmark
Page 47 and 48: Benchmark
Page 49 and 50: Custom Flows Verilog Design Yosys V
Page 51 and 52: cycle3.tpl (setlogic QF_UFBV) ; i
Page 53: cycle3.tpl $ yosys ql cycle3.yslo
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Formal Verification with Yosys-SMTBMC Clifford Wolf

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