Formal Verification with Yosys-SMTBMC Clifford Wolf

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Simulation vs. Verification Simulation checks only some of the reachable states. For non-trivial designs it is impossible to check all reachable states using simulation. Verification uses symbolic methods to check all reachable states. simulation traces initial states reachable state reachable state that violates assertions
Why Formal Verification? ● Prove that a design is correct – Usually hard to achieve. – Typically only done for critical applications such as medical or aerospace. – Requires a full formal spec of correct behavior. ● Bughunting – Only requires partial specs. (The more the better of course.) – OK to replace one large proof with many smaller individual checks without proving that the smaller checks actually cover the original spec entirely. – Tends to find the most obscure bugs that would be really hard to find otherwise. – Finds bugs in a controlled environment. – Be the hunter, not the hunted! ● Optimization – No formal spec? Simply use the unoptimized version of the design as reference when working on optimizations.
Page 1 and 2: Formal Verification with Yosys-SMTB
Page 3: Availability of various EDA tools f
Page 7 and 8: Yosys-SMTBMC Examples ● Slides an
Page 9 and 10: Hello World yosyssmtbmc hello1.sm
Page 11 and 12: Immediate assertions, Concurrent as
Page 13 and 14: Hello Test-Bench module hello(input
Page 15 and 16: Bounded vs. Unbounded Methods ●
Page 17 and 18: Temporal Induction Assuming we have
Page 19 and 20: SAT Solving and SMT Solving ● Sat
Page 21 and 22: Yosys-SMTBMC Flow Verilog Design Ve
Page 23 and 24: eachable states assertions
Page 25 and 26: demo1.v
Page 27 and 28: demo2.v $ make demo2 yosyssmtbmc
Page 29 and 30: memcmp.v module memory1 ( input clk
Page 31 and 32: memcmp.v module memcmp ( input clk,
Page 33 and 34: axicheck.v // only deassert “vali
Page 35 and 36: Bounded Liveness Properties ● Saf
Page 37 and 38: multiclk.v module multiclk(input cl
Page 39 and 40: setreset.v module setreset(input cl
Page 41 and 42: abccex.v module abccex(input clk, i
Page 43 and 44: Benchmark ● See benchmark.zip and
Page 45 and 46: Benchmark
Page 47 and 48: Benchmark
Page 49 and 50: Custom Flows Verilog Design Yosys V
Page 51 and 52: cycle3.tpl (setlogic QF_UFBV) ; i
Page 53 and 54: cycle3.tpl $ yosys ql cycle3.yslo
Page 55 and 56:
Future Work ● Limited support for
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Formal Verification with Yosys-SMTBMC Clifford Wolf

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