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setreset.v<br />
yosys ql setreset.yslog \<br />
p 'read_verilog formal setreset.v' \<br />
p 'prep top setreset nordff' \<br />
p 'clk2fflogic; opt_clean' \<br />
p 'write_smt2 setreset.smt2'<br />
Warning: Complex async reset for dff `\q1'.<br />
yosyssmtbmc s boolector setreset.smt2<br />
## 0 0:00:00 Solver: boolector<br />
## 0 0:00:00 Checking asserts in step 0..<br />
...<br />
## 0 0:00:00 Checking asserts in step 19..<br />
## 0 0:00:00 Status: PASSED<br />
yosyssmtbmc i s boolector setreset.smt2<br />
## 0 0:00:00 Solver: boolector<br />
## 0 0:00:00 Trying induction in step 20..<br />
## 0 0:00:00 Trying induction in step 19..<br />
## 0 0:00:00 Temporal induction successful.<br />
## 0 0:00:00 Status: PASSED