Formal Verification with Yosys-SMTBMC Clifford Wolf

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axicheck2.v Instantiate two copies of the UUT, let them have independent “ready” signals, but force them to be equal when “valid” is active: if (mem_axi_awvalid_0) assume(mem_axi_awready_0 == mem_axi_awready_1); This must not have any effect on the “valid” and “data” signals: assert(mem_axi_awvalid_0 == mem_axi_awvalid_1); assert(mem_axi_awaddr_0 == mem_axi_awaddr_1 ); assert(mem_axi_awprot_0 == mem_axi_awprot_1 ); Instead of resetting both UUT in the initial state, we just force them to be equal in the initial state (see axicheck2.smtc): initial assume (= [uut_0] [uut_1]) (An SMT solver <strong>with</strong> true UF support is needed in order to compare hierarchical cells like this.)
Bounded Liveness Properties ● Safety properties are asserting that certain states are unreachable from a set of initial states. – This are the properties we have been looking at so far. ● Liveness properties are asserting that certain state inevitable are going to be reached from a set of initial states. – Checking liveness is hard. – Usually this is used to prove that the circuit will always make progress, i.e. that the circuit cannot get stuck somehow. – In many cases bounded liveness properties are actually more useful: Assert that the target state is going to be reached <strong>with</strong>in a given timeout: integer timeout = 0; always @(posedge clk) if (axis_valid && !axis_ready) timeout
Page 1 and 2: Formal Verification with Yosys-SMTB
Page 3 and 4: Availability of various EDA tools f
Page 5 and 6: Why Formal Verification? ● Prove
Page 7 and 8: Yosys-SMTBMC Examples ● Slides an
Page 9 and 10: Hello World yosyssmtbmc hello1.sm
Page 11 and 12: Immediate assertions, Concurrent as
Page 13 and 14: Hello Test-Bench module hello(input
Page 15 and 16: Bounded vs. Unbounded Methods ●
Page 17 and 18: Temporal Induction Assuming we have
Page 19 and 20: SAT Solving and SMT Solving ● Sat
Page 21 and 22: Yosys-SMTBMC Flow Verilog Design Ve
Page 23 and 24: eachable states assertions
Page 25 and 26: demo1.v
Page 27 and 28: demo2.v $ make demo2 yosyssmtbmc
Page 29 and 30: memcmp.v module memory1 ( input clk
Page 31 and 32: memcmp.v module memcmp ( input clk,
Page 33: axicheck.v // only deassert “vali
Page 37 and 38: multiclk.v module multiclk(input cl
Page 39 and 40: setreset.v module setreset(input cl
Page 41 and 42: abccex.v module abccex(input clk, i
Page 43 and 44: Benchmark ● See benchmark.zip and
Page 45 and 46: Benchmark
Page 47 and 48: Benchmark
Page 49 and 50: Custom Flows Verilog Design Yosys V
Page 51 and 52: cycle3.tpl (setlogic QF_UFBV) ; i
Page 53 and 54: cycle3.tpl $ yosys ql cycle3.yslo
Page 55 and 56: Future Work ● Limited support for

Formal Verification with Yosys-SMTBMC Clifford Wolf

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