Formal Verification with Yosys-SMTBMC Clifford Wolf

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multiclk.v yosys ql multiclk.yslog \ p 'read_verilog formal multiclk.v' \ p 'prep top multiclk nordff' \ p 'clk2fflogic; opt_clean' \ p 'write_smt2 multiclk.smt2' yosyssmtbmc s boolector multiclk.smt2 ## 0 0:00:00 Solver: boolector ## 0 0:00:00 Checking asserts in step 0.. ... ## 0 0:00:00 Checking asserts in step 19.. ## 0 0:00:00 Status: PASSED yosyssmtbmc i s boolector multiclk.smt2 ## 0 0:00:00 Solver: boolector ## 0 0:00:00 Trying induction in step 20.. ## 0 0:00:00 Trying induction in step 19.. ## 0 0:00:00 Temporal induction successful. ## 0 0:00:00 Status: PASSED
setreset.v module setreset(input clk, input set, rst, d, output q1, q2); reg q1 = 0; always @(posedge clk, posedge set, posedge rst) if (rst) q1
Page 1 and 2: Formal Verification with Yosys-SMTB
Page 3 and 4: Availability of various EDA tools f
Page 5 and 6: Why Formal Verification? ● Prove
Page 7 and 8: Yosys-SMTBMC Examples ● Slides an
Page 9 and 10: Hello World yosyssmtbmc hello1.sm
Page 11 and 12: Immediate assertions, Concurrent as
Page 13 and 14: Hello Test-Bench module hello(input
Page 15 and 16: Bounded vs. Unbounded Methods ●
Page 17 and 18: Temporal Induction Assuming we have
Page 19 and 20: SAT Solving and SMT Solving ● Sat
Page 21 and 22: Yosys-SMTBMC Flow Verilog Design Ve
Page 23 and 24: eachable states assertions
Page 25 and 26: demo1.v
Page 27 and 28: demo2.v $ make demo2 yosyssmtbmc
Page 29 and 30: memcmp.v module memory1 ( input clk
Page 31 and 32: memcmp.v module memcmp ( input clk,
Page 33 and 34: axicheck.v // only deassert “vali
Page 35 and 36: Bounded Liveness Properties ● Saf
Page 37: multiclk.v module multiclk(input cl
Page 41 and 42: abccex.v module abccex(input clk, i
Page 43 and 44: Benchmark ● See benchmark.zip and
Page 45 and 46: Benchmark
Page 47 and 48: Benchmark
Page 49 and 50: Custom Flows Verilog Design Yosys V
Page 51 and 52: cycle3.tpl (setlogic QF_UFBV) ; i
Page 53 and 54: cycle3.tpl $ yosys ql cycle3.yslo
Page 55 and 56: Future Work ● Limited support for

Formal Verification with Yosys-SMTBMC Clifford Wolf

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