Formal Verification with Yosys-SMTBMC Clifford Wolf

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Installing Yosys-SMTBMC (Ubuntu 16.04) ● Install prerequisites: – sudo aptget install buildessential clang bison flex \ libreadlinedev gawk tcldev libffidev git mercurial \ graphviz xdot pkgconfig python3 ● Build and install Yosys (incl. Yosys-SMTBMC): – git clone https://github.com/cliffordwolf/yosys – cd yosys; make – sudo make install ● Build and install the Z3 SMT solver: – git clone https://github.com/Z3Prover/z3 – cd z3; python scripts/mk_make.py – cd build; make – sudo make install
Yosys-SMTBMC Examples ● Slides and examples from this presentation: – http://www.clifford.at/papers/2016/yosys-smtbmc/ ● Some simple examples are bundled with Yosys: – See examples/smtbmc/ in Yosys source code ● See PicoRV32 for real-world example: – https://github.com/cliffordwolf/picorv32 – Run “make check” to verify properties in picorv32.v – See scripts/smtbmc/ for more advanced checks
Page 1 and 2: Formal Verification with Yosys-SMTB
Page 3 and 4: Availability of various EDA tools f
Page 5: Why Formal Verification? ● Prove
Page 9 and 10: Hello World yosyssmtbmc hello1.sm
Page 11 and 12: Immediate assertions, Concurrent as
Page 13 and 14: Hello Test-Bench module hello(input
Page 15 and 16: Bounded vs. Unbounded Methods ●
Page 17 and 18: Temporal Induction Assuming we have
Page 19 and 20: SAT Solving and SMT Solving ● Sat
Page 21 and 22: Yosys-SMTBMC Flow Verilog Design Ve
Page 23 and 24: eachable states assertions
Page 25 and 26: demo1.v
Page 27 and 28: demo2.v $ make demo2 yosyssmtbmc
Page 29 and 30: memcmp.v module memory1 ( input clk
Page 31 and 32: memcmp.v module memcmp ( input clk,
Page 33 and 34: axicheck.v // only deassert “vali
Page 35 and 36: Bounded Liveness Properties ● Saf
Page 37 and 38: multiclk.v module multiclk(input cl
Page 39 and 40: setreset.v module setreset(input cl
Page 41 and 42: abccex.v module abccex(input clk, i
Page 43 and 44: Benchmark ● See benchmark.zip and
Page 45 and 46: Benchmark
Page 47 and 48: Benchmark
Page 49 and 50: Custom Flows Verilog Design Yosys V
Page 51 and 52: cycle3.tpl (setlogic QF_UFBV) ; i
Page 53 and 54: cycle3.tpl $ yosys ql cycle3.yslo
Page 55 and 56: Future Work ● Limited support for

Formal Verification with Yosys-SMTBMC Clifford Wolf

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