Formal Verification with Yosys-SMTBMC Clifford Wolf

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Supported SMT Solvers ● ● In principle, every solver that supports the SMT-LIB2 language, model generation, and incremental solving is supported. (Solver with QF_AUFBV support is recommended.) Yosys-SMTBMC has been tested with the following solvers: – Z3, CVC4, Yices2, MathSAT5, Boolector – Source code is available for all those solvers, but not all of them are FOSS. – Different solvers may perform differently for different designs. Supporting more than one solver is key! Solver License PicoRV32 * make check Z3 permissive 94 seconds CVC4 copyleft ≈ 3.4 • 10 11 hours Yices2 non-commercial 10 seconds Boolector non-commercial 65 seconds MathSAT5 non-commercial 345 seconds * CPU time on AMD FX-8150 at 3600 MHz, PicoRV32 git rev 7f946d0. Software versions: Z3 4.4.0, CVC4 1.4, Yices 2.5.1, MathSAT 5.3.13, Boolector 2.2.0
Bounded vs. Unbounded Methods ● ● Bounded methods only consider states reachable within N time steps from initial states. Unbounded methods consider all reachable states, regardless of the number of time steps required to reach them from the initial states. ● ● BMC (bounded model check) is a bounded method. Temporal Induction can be used as a simple method for performing unbounded proofs with a bounded solver.
Page 1 and 2: Formal Verification with Yosys-SMTB
Page 3 and 4: Availability of various EDA tools f
Page 5 and 6: Why Formal Verification? ● Prove
Page 7 and 8: Yosys-SMTBMC Examples ● Slides an
Page 9 and 10: Hello World yosyssmtbmc hello1.sm
Page 11 and 12: Immediate assertions, Concurrent as
Page 13: Hello Test-Bench module hello(input
Page 17 and 18: Temporal Induction Assuming we have
Page 19 and 20: SAT Solving and SMT Solving ● Sat
Page 21 and 22: Yosys-SMTBMC Flow Verilog Design Ve
Page 23 and 24: eachable states assertions
Page 25 and 26: demo1.v
Page 27 and 28: demo2.v $ make demo2 yosyssmtbmc
Page 29 and 30: memcmp.v module memory1 ( input clk
Page 31 and 32: memcmp.v module memcmp ( input clk,
Page 33 and 34: axicheck.v // only deassert “vali
Page 35 and 36: Bounded Liveness Properties ● Saf
Page 37 and 38: multiclk.v module multiclk(input cl
Page 39 and 40: setreset.v module setreset(input cl
Page 41 and 42: abccex.v module abccex(input clk, i
Page 43 and 44: Benchmark ● See benchmark.zip and
Page 45 and 46: Benchmark
Page 47 and 48: Benchmark
Page 49 and 50: Custom Flows Verilog Design Yosys V
Page 51 and 52: cycle3.tpl (setlogic QF_UFBV) ; i
Page 53 and 54: cycle3.tpl $ yosys ql cycle3.yslo
Page 55 and 56: Future Work ● Limited support for

Formal Verification with Yosys-SMTBMC Clifford Wolf

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