Formal Verification with Yosys-SMTBMC Clifford Wolf

More documents

Recommendations

Info

Benchmark Solver performance for stand-alone SMT2 files generated from yosys-smtbmc for the different supported logics. The SMT2 benchmark files have been submitted for SMTCOMP. z3 Benchmark “PicoRV32 check” yices z3 Benchmark “PicoRV32 comp” yices z3 Benchmark “PicoRV32 hard” yices boolector boolector boolector QF_AUFBV 158 8 ----- 668 279 ----- 14/17 5326 ----- QF_UFBV 164 10 ----- 493 64 ----- 13/17 14/17 ----- QF_UF 13 7 ----- 103 29 ----- 15/17 15/17 ----- QF_ABV 169 6 21 744 152 9 14/17 5214 623 QF_BV 173 7 37 547 48 11 13/17 14/17 7168 1234 … Benchmark completed after 1234 seconds 12/17 … Benchmark reached timeout, completed 12 of 17 steps Timeout was 8000 seconds (about 2 hours 15 minutes) for all benchmarks
Custom Flows Verilog Design <strong>Yosys</strong> Verilog Asserts SMT-LIB2 Code ? ? ? SMT-LIB2 Solver Options for writing custom proofs: - Hand-written SMT2 code - Custom python script using smtio.py (the python lib implementing most of yosyssmtbmc) - Any other app using any SMT- LIB2 solver (e.g. using C/C++ API for proofs that involve many (checksat) calls.
Page 1 and 2: Formal Verification with Yosys-SMTB
Page 3 and 4: Availability of various EDA tools f
Page 5 and 6: Why Formal Verification? ● Prove
Page 7 and 8: Yosys-SMTBMC Examples ● Slides an
Page 9 and 10: Hello World yosyssmtbmc hello1.sm
Page 11 and 12: Immediate assertions, Concurrent as
Page 13 and 14: Hello Test-Bench module hello(input
Page 15 and 16: Bounded vs. Unbounded Methods ●
Page 17 and 18: Temporal Induction Assuming we have
Page 19 and 20: SAT Solving and SMT Solving ● Sat
Page 21 and 22: Yosys-SMTBMC Flow Verilog Design Ve
Page 23 and 24: eachable states assertions
Page 25 and 26: demo1.v
Page 27 and 28: demo2.v $ make demo2 yosyssmtbmc
Page 29 and 30: memcmp.v module memory1 ( input clk
Page 31 and 32: memcmp.v module memcmp ( input clk,
Page 33 and 34: axicheck.v // only deassert “vali
Page 35 and 36: Bounded Liveness Properties ● Saf
Page 37 and 38: multiclk.v module multiclk(input cl
Page 39 and 40: setreset.v module setreset(input cl
Page 41 and 42: abccex.v module abccex(input clk, i
Page 43 and 44: Benchmark ● See benchmark.zip and
Page 45 and 46: Benchmark
Page 47: Benchmark
Page 51 and 52: cycle3.tpl (setlogic QF_UFBV) ; i
Page 53 and 54: cycle3.tpl $ yosys ql cycle3.yslo
Page 55 and 56: Future Work ● Limited support for

Formal Verification with Yosys-SMTBMC Clifford Wolf

You also want an ePaper? Increase the reach of your titles

Delete template?

Save as template?