Formal Verification with Yosys-SMTBMC Clifford Wolf

Formal Test-Benches
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Often a “test-bench” is used for formal verification, similar to simulation.
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For simple cases, i.e. verification of assert() statements in a regular design,
the test-bench is a simple wrapper for the module under test.
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Usually the test-bench contains a few additional assume() or restrict()
statements that make sure the module under test is properly reset.
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In more complex setups, the “test-bench” can be an elaborate design in itself,
constructing a sophisticated proof around one or multiple modules under test.
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See scripts/smtbmc/ in the PicoRV32 github repository for such examples.