Formal Verification with Yosys-SMTBMC Clifford Wolf

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Temporal Induction induction length must be at least 5 loop must be broken, using stronger asserts or by adding restrictions (assumptions) no problem here reachable states assertions
SAT Solving and SMT Solving ● Satisfiability (SAT) Solvers – Input: system of boolean formulas – Output: SAT/UNSAT, Witness (aka “model” for SAT) ● SAT Modulo Theory (SMT) Solvers – Combine SAT solving with higher-level theories, such as: ● ● ● ● A: Arrays with extensionality UF: Uninterpreted functions BV: Bit vectors with arithmetic I: Unbound integer arithmetic, … – Usually significantly faster than plain SAT solvers when higher-level theories are used to preserve the problem structure. (e.g. using (bvadd) instead of system of boolean formulas for adder circuit) ● SMT-LIB2 File Format – There is an annual competition for SMT solvers called SMT-COMP – All benchmarks used in SMT-COMP are in the SMT-LIB2 file format – So practically all SMT solvers support the SMT-LIB2 file format – Yosys-SMTBMC can use any SMT solver with support for the SMT-LIB2 QF_AUFBV logic
Page 1 and 2: Formal Verification with Yosys-SMTB
Page 3 and 4: Availability of various EDA tools f
Page 5 and 6: Why Formal Verification? ● Prove
Page 7 and 8: Yosys-SMTBMC Examples ● Slides an
Page 9 and 10: Hello World yosyssmtbmc hello1.sm
Page 11 and 12: Immediate assertions, Concurrent as
Page 13 and 14: Hello Test-Bench module hello(input
Page 15 and 16: Bounded vs. Unbounded Methods ●
Page 17: Temporal Induction Assuming we have
Page 21 and 22: Yosys-SMTBMC Flow Verilog Design Ve
Page 23 and 24: eachable states assertions
Page 25 and 26: demo1.v
Page 27 and 28: demo2.v $ make demo2 yosyssmtbmc
Page 29 and 30: memcmp.v module memory1 ( input clk
Page 31 and 32: memcmp.v module memcmp ( input clk,
Page 33 and 34: axicheck.v // only deassert “vali
Page 35 and 36: Bounded Liveness Properties ● Saf
Page 37 and 38: multiclk.v module multiclk(input cl
Page 39 and 40: setreset.v module setreset(input cl
Page 41 and 42: abccex.v module abccex(input clk, i
Page 43 and 44: Benchmark ● See benchmark.zip and
Page 45 and 46: Benchmark
Page 47 and 48: Benchmark
Page 49 and 50: Custom Flows Verilog Design Yosys V
Page 51 and 52: cycle3.tpl (setlogic QF_UFBV) ; i
Page 53 and 54: cycle3.tpl $ yosys ql cycle3.yslo
Page 55 and 56: Future Work ● Limited support for

Formal Verification with Yosys-SMTBMC Clifford Wolf

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