Formal Verification with Yosys-SMTBMC Clifford Wolf

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Preserving Problem Structure ● ● Preserving problem structure helps SMT solvers to excel at their task. Yosys-SMTBMC preserves problem structure using the following techniques (using the SMT-LIB2 QF_AUFBV theory): – No synthesis to gate level logic (instead use SMT-LIB2 Bit vectors) ● Preserves arithmetic and word-wide operations – No synthesis of memories to circuits of FFs and MUXes (instead use Arrays) ● Vastly reduces the model size for arrays with more elements than time steps in the BMC – No flattening of design hierarchy (instead use uninterpreted functions)* ● Preserves structure when a module is instantiated many times – No unrolling of time steps (instead use uninterpreted functions)* ● Preserves structure in deep bounded model checks ● Ultimately the SMT solver will have to perform this transformations in one way or another. But for many reasons it is better to let the solver do them. * Use “yosys-smtbmc –unroll” to create SMT2 code that is already unrolled, e.g. for solvers without UF theory support. In some cases UF-capable solvers can be faster on pre-unrolled problems. See also benchmark results at the end of this slide set.
Yosys-SMTBMC Flow Verilog Design Verilog Asserts Yosys PASS / FAIL Constraints File SMT-LIB2 Code Yosys-SMTBMC SMT-LIB2 Solver VCD File Verilog Testbench Constraints File Trace / counterexample formats
Page 1 and 2: Formal Verification with Yosys-SMTB
Page 3 and 4: Availability of various EDA tools f
Page 5 and 6: Why Formal Verification? ● Prove
Page 7 and 8: Yosys-SMTBMC Examples ● Slides an
Page 9 and 10: Hello World yosyssmtbmc hello1.sm
Page 11 and 12: Immediate assertions, Concurrent as
Page 13 and 14: Hello Test-Bench module hello(input
Page 15 and 16: Bounded vs. Unbounded Methods ●
Page 17 and 18: Temporal Induction Assuming we have
Page 19: SAT Solving and SMT Solving ● Sat
Page 23 and 24: eachable states assertions
Page 25 and 26: demo1.v
Page 27 and 28: demo2.v $ make demo2 yosyssmtbmc
Page 29 and 30: memcmp.v module memory1 ( input clk
Page 31 and 32: memcmp.v module memcmp ( input clk,
Page 33 and 34: axicheck.v // only deassert “vali
Page 35 and 36: Bounded Liveness Properties ● Saf
Page 37 and 38: multiclk.v module multiclk(input cl
Page 39 and 40: setreset.v module setreset(input cl
Page 41 and 42: abccex.v module abccex(input clk, i
Page 43 and 44: Benchmark ● See benchmark.zip and
Page 45 and 46: Benchmark
Page 47 and 48: Benchmark
Page 49 and 50: Custom Flows Verilog Design Yosys V
Page 51 and 52: cycle3.tpl (setlogic QF_UFBV) ; i
Page 53 and 54: cycle3.tpl $ yosys ql cycle3.yslo
Page 55 and 56: Future Work ● Limited support for

Formal Verification with Yosys-SMTBMC Clifford Wolf

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