KOMPRESI CITRA JPEG BERBASIS FPGA XILINX SPARTAN-3E ...

Source code root enkoder JPEG (jpeg-ram.vhd)library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_signed.all;use ieee.numeric_std.all;LIBRARY UNISIM;use UNISIM.VCOMPONENTS.ALL;entity jpeg_ram isgeneric(lebar_in:integer:=7;lebar_ot:integer:=8;lebar_max:integer:=13--lebar bus data memori);port(clk: in std_logic;clk2: in std_logic;rst: in std_logic;-- rst2: in std_logic;en: in std_logic;dat_in: in std_logic_vector(lebar_in downto 0);-- clko: out std_logic;data_rdy: out std_logic;par_rdy: out std_logic;serial_out:out std_logic);end jpeg_ram;architecture behav of jpeg_ram iscomponent jpegcoder isgeneric(lebar_in:integer:=7;lebar_ot:integer:=8;lebar_max:integer:=13--lebar bus data memori);port(clk: in std_logic;rst: in std_logic;en: in std_logic;dat_in: in std_logic_vector(lebar_in downto 0);cat:out std_logic_vector(3 downto 0);len:out std_logic_vector(3 downto 0);sym:out std_logic_vector(15 downto 0);huff:out std_logic_vector(15 downto 0);addr:out std_logic_vector(7 downto 0);en_out: out std_logic;--en_serial:out std_logic;valid:out std_logic);end component;component coderam isgeneric(B - 2