KOMPRESI CITRA JPEG BERBASIS FPGA XILINX SPARTAN-3E ...

component ac_coder isport(clk: in std_logic;clr: in std_logic;dc: in std_logic;data_in:in std_logic_vector(15 downto 0);cat:out std_logic_vector(3 downto 0);len:out std_logic_vector(3 downto 0);sym:out std_logic_vector(15 downto 0);huff:out std_logic_vector(15 downto 0);valid:out std_logic);end component;component huff_dc isport(dc_cat: in std_logic_vector(3 downto 0);dc_code: out std_logic_vector(15 downto 0);len: out std_logic_vector(3 downto 0));end component;component codemux isport(alen: in std_logic_vector(3 downto 0);blen: in std_logic_vector(3 downto 0);ahuff: in std_logic_vector(15 downto 0);bhuff: in std_logic_vector(15 downto 0);sel: in std_logic;len: out std_logic_vector(3 downto 0);huff: out std_logic_vector(15 downto 0));end component;signal tmpcat: std_logic_vector(3 downto 0);signal aclen: std_logic_vector(3 downto 0);signal dclen: std_logic_vector(3 downto 0);signal achuff: std_logic_vector(15 downto 0);signal dchuff: std_logic_vector(15 downto 0);begincat