KOMPRESI CITRA JPEG BERBASIS FPGA XILINX SPARTAN-3E ...

signal d0: std_logic_vector(k downto 0);signal d1: std_logic_vector(k downto 0);signal d2: std_logic_vector(k downto 0);signal d3: std_logic_vector(k downto 0);signal d4: std_logic_vector(k downto 0);signal d5: std_logic_vector(k downto 0);signal d6: std_logic_vector(k downto 0);signal d7: std_logic_vector(k downto 0);signal d8: std_logic_vector(k downto 0);signal e0: std_logic_vector(h downto 0);signal e1: std_logic_vector(h downto 0);signal e2: std_logic_vector(h downto 0);signal e3: std_logic_vector(h downto 0);signal e4: std_logic_vector(h downto 0);signal e5: std_logic_vector(h downto 0);signal e6: std_logic_vector(h downto 0);signal e7: std_logic_vector(h downto 0);signal e8: std_logic_vector(h downto 0);signal f0: std_logic_vector(h downto 0);signal f1: std_logic_vector(h downto 0);signal f2: std_logic_vector(h downto 0);signal f3: std_logic_vector(h downto 0);signal f4: std_logic_vector(h downto 0);signal f5: std_logic_vector(h downto 0);signal f6: std_logic_vector(h downto 0);signal f7: std_logic_vector(h downto 0);signal s0: std_logic_vector(h downto 0);signal s1: std_logic_vector(h downto 0);signal s2: std_logic_vector(h downto 0);signal s3: std_logic_vector(h downto 0);signal s4: std_logic_vector(h downto 0);signal s5: std_logic_vector(h downto 0);signal s6: std_logic_vector(h downto 0);signal s7: std_logic_vector(h downto 0);signal ofset0: std_logic_vector(k downto 0);signal ofset1: std_logic_vector(k downto 0);signal ofset2: std_logic_vector(k downto 0);signal ofset3: std_logic_vector(k downto 0);signal ofset4: std_logic_vector(k downto 0);signal ofset5: std_logic_vector(k downto 0);signal ofset6: std_logic_vector(k downto 0);signal ofset7: std_logic_vector(k downto 0);signal out_en:std_logic;signal cnt_in:std_logic_vector(7 downto 0);signal cntr_out:std_logic_vector(7 downto 0);begincnt_out