KOMPRESI CITRA JPEG BERBASIS FPGA XILINX SPARTAN-3E ...

st: in std_logic;dc: in std_logic;din: in std_logic_vector(lebar_ot downto 0);dout: out std_logic_vector(lebar_ot downto 0));end dpcm;architecture behav of dpcm iscomponent mux21 isport(a: in std_logic_vector(8 downto 0);b: in std_logic_vector(8 downto 0);sel: in std_logic;y: out std_logic_vector(8 downto 0));end component;signal ctr: std_logic_vector(lebar_ctr downto 0);signal dctemp: std_logic_vector(lebar_ot downto 0);signal mulai: std_logic;signal diff: std_logic_vector(lebar_ot downto 0);beginmuxpcm:mux21 port map(din,diff,dc,dout);diff