KOMPRESI CITRA JPEG BERBASIS FPGA XILINX SPARTAN-3E ...

n:integer:=10;--MSB data inputk:integer:=13;--MSB outputh:integer:=27;--MSB hasil kalip:integer:=12);--pengali dikalikan 2^12port(clk: in std_logic;rst: in std_logic;en_dct: in std_logic;vin: in std_logic_vector(n downto 0);cnt_out: out std_logic_vector(3 downto 0);en_out: out std_logic;vout:out std_logic_vector(k downto 0));end component;component memori isgeneric(lebar_data:integer:=13--lebar bus data memori);port(addr_baca: in std_logic_vector(7 downto 0);addr_tls: in std_logic_vector(7 downto 0);data_tls: in std_logic_vector(lebar_data downto 0);data_baca: out std_logic_vector(lebar_data downto 0);we:in std_logic;clk: in std_logic);end component;component quantizer isgeneric(lebar_dct:integer:=13;lebar_rom:integer:=7;--lebar bus data romlebar_out:integer:=8;kali:integer:=21);port(dct_in:in std_logic_vector(lebar_dct downto 0);rom_in:in std_logic_vector(lebar_rom downto 0);quant_out: out std_logic_vector(lebar_out downto 0));end component;component myqROM isgeneric( width: integer:=8; -- lebar bit tiap alamatdepth: integer:=64; -- ada berapa byte alamataddr: integer:=6); -- lebar bus alamatport(--din: in std_logic_vector(width-1 downto 0);dout: out std_logic_vector(width-1 downto 0);address: in std_logic_vector(addr-1 downto 0)--rd: in std_logic);end component;signal dout: std_logic_vector(lebar_max downto 0);--keluaran memorisignal dct_out: std_logic_vector(10 downto 0);--keluaran dctaB - 8