Artificial Intelligence and Soft Computing: Behavioral ... - Arteimi.info

For the sake of convenience, the pipelining and parallelism of different
modulus is presented in fig. 22.18. An estimation of the cycle time for firing a
transition is computed in fig. 22.19 following the pipelining of the stages in
fig. 22.18. It is evident from fig. 22.19 that the TSF works in parallel with the
pipelined stages comprising of THF, PTVVM and Matcher or THF, PTVVM
and FPS in sequence. The matcher and the FPS start working only when the
PTVVM completes the current task. The time required for the matcher being
larger than that of FPS we consider the time required by the matcher only
following THF and PTVVM. It is also clear from the figure that the matcher
finishes its tasks at time e, which is larger than the time d required by the
TSF. An additional 2 gate delay followed by a few memory access cycles plus
gate delay makes the total cycle time equal to g, which is the effective cycle
time for firing a transition. The time requirement for each unit is shown in the
fig. 22.19 itself and needs no further clarification.
1 Memory
access
THF
TSF
PTVVM Matcher
25 Tc 10 gate delay
FPS
2 gate delay
Delay
Fig. 22.18: Pipelining among the major modules of the architecture for
the execution of FOL programs; each circuit corresponds to
one transition.
Since a number of transitions are concurrently firable, it is expected that
the execution of a complete logic program will require an integer multiple of
this transition firing cycle time. Assuming a clock cycle time equal to Tc and
ignoring smaller gate delays, it has been found that the total cycle time
required for firing a transition is 25 Tc .
Thus assuming a 100M-Hz clock frequency, the cycle time for one
transition is equal to 25x10 -8 S = 250 nS (nanosecond ). Now for the sample
logic program represented by the Petri net of fig. 22.17, the total time for