E200Z1RM, e200z1 Power Architecture Ž Core - Reference Manual

Contents
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Number Title
e200z1 Power Architecture Core Reference Manual, Rev. 0
Page
Number
Clock 2 (C2): 38
Clock 3 (C3): 38
Clock 4 (C4): 38
7.4.1.2 Read Transfer with Wait State ............................................................................... 7-38
7.4.1.3 Basic Write Transfer Cycles .................................................................................. 7-40
Clock 1 (C1): 40
Clock 2 (C2): 41
Clock 3 (C3): 41
Clock 4 (C4): 41
7.4.1.4 Write Transfer with Wait States............................................................................. 7-41
7.4.1.5 Read and Write Transfers ...................................................................................... 7-43
7.4.1.6 Misaligned Accesses.............................................................................................. 7-47
7.4.1.7 Burst Accesses ....................................................................................................... 7-50
7.4.1.8 Address Retraction................................................................................................. 7-56
7.4.1.9 Error Termination Operation ................................................................................. 7-58
7.4.2 Power Management ................................................................................................... 7-61
7.4.3 Interrupt Interface ...................................................................................................... 7-62
7.4.4 Time Base Interface ................................................................................................... 7-64
7.4.5 JTAG Test Interface ................................................................................................... 7-65
Chapter 8
Power Management
8.1 Power Management ......................................................................................................... 8-1
8.1.1 Active State.................................................................................................................. 8-1
8.1.2 Waiting State................................................................................................................ 8-1
8.1.3 Halted State.................................................................................................................. 8-1
8.1.4 Stopped State ............................................................................................................... 8-2
8.1.5 Power Management Pins ............................................................................................. 8-2
8.1.6 Power Management Control Bits................................................................................. 8-3
8.1.7 Software Considerations for Power Management using Wait Instructions ................. 8-3
8.1.8 Software Considerations for Power Management Using Doze, Nap, or Sleep ........... 8-3
8.1.9 Debug Considerations for Power Management........................................................... 8-4
Chapter 9
Debug Support
9.1 Overview.......................................................................................................................... 9-1
9.1.1 Software Debug Facilities............................................................................................ 9-1
9.1.1.1 Power Architecture Book E Compatibility.............................................................. 9-2
9.1.2 Additional Debug Facilities......................................................................................... 9-2
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