E200Z1RM, e200z1 Power Architecture Ž Core - Reference Manual

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Tables Table Number Title e200z1 Power Architecture Core Reference Manual, Rev. 0 Page Number xx Freescale Semiconductor
Chapter 1 e200z1 Overview 1.1 Overview of the e200z1 Cores The e200 processor family is a set of CPU cores that implement low-cost versions of the Power Architecture Book E architecture. e200 processors are designed for deeply embedded control applications, which require low cost solutions rather than maximum performance. The processors integrate an integer execution unit, branch control unit, instruction fetch and load/store units, and a multi-ported register file capable of sustaining three read and two write operations per clock. Most integer instructions execute in a single clock cycle. Branch target prefetching is performed by the branch unit to allow single-cycle branches in some cases. The e200z1 core is a single-issue, 32-bit Power Architecture Book E compliant design with 32-bit general purpose registers (GPRs). Power Architecture Book E floating-point instructions are not supported by e200 in hardware, but are trapped and may be emulated by software.All arithmetic instructions that execute in the core operate on data in the general purpose registers (GPRs). In addition to the base Power Architecture Book E instruction set support, the core also implements the VLE (variable-length encoding) APU, providing improved code density. The VLE APU is further documented in the PowerPC VLE APU Definition, Version 1.01, a separate document. In the remainder of this document, the e200z1 core is also referred to as the “e200z1 core” or “e200 core” when referring to the whole e200 family. 1.1.1 Features The following is a list of some of the key features of the e200z1 core: 32-bit Power Architecture Book E programmer’s model Single issue, 32-bit CPU Implements the VLE APU for reduced code footprint In-order execution and retirement Precise exception handling Branch processing unit — Dedicated branch address calculation adder — Branch acceleration using Branch Target Buffer Supports independent instruction and data accesses to different memory subsystems, such as SRAM and Flash memory via independent Instruction and Data bus interface units (BIUs). Load/store unit e200z1 Power Architecture Core Reference Manual, Rev. 0 Freescale Semiconductor 1-1
Page 1 and 2: e200z1 Power Architecture Core Refe
Page 3 and 4: Contents Paragraph Number Title Con
Page 5 and 6: Contents Paragraph Number Title e20
Page 13 and 14: Figures Figure Number Title e200z1
Page 15 and 16: Figures Figure Number Title e200z1
Page 17 and 18: Tables Table Number Title e200z1 Po
Page 19: Tables Table Number Title e200z1 Po
Page 27 and 28: Chapter 2 Register Model This secti
Page 29 and 30: PSU Registers 1 PSU PSCR PSSR PSHR
Page 35 and 36: 17 (49) 18 (50) 19 (51) 20 (52) 21
Page 39 and 40: 8 (40) 9 (41) 10 (42) 11 (43) 12 (4
Page 43 and 44: 2.4.9 Timer Status Register (TSR) e
Page 45 and 46: 14 ICR Interrupt Inputs Clear Reser
Page 47 and 48: 2.4.13 Branch Unit Control and Stat
Page 49 and 50: Table 2-14. Additional Synchronizat
Page 51 and 52: Mnemonic Name Table 2-15. Special P
Page 53 and 54: Table 2-16. Reset Settings for e200
Page 55 and 56: Chapter 3 Instruction Model This ch
Page 57 and 58: 3.5 Memory Access Alignment Support
Page 63 and 64: 3.12.1 Instruction Index Sorted by
Page 65 and 66: Format Primary (Inst 0:5) Opcode e2
Page 67 and 68: Format Primary (Inst 0:5) Opcode X
Page 69 and 70: Format Primary (Inst 0:5) Opcode X
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Format Primary (Inst 0:5) Opcode XL
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Format Primary (Inst 0:5) Opcode Ta
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Format Primary (Inst0:5) Opcode Ext
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e200z1 Power Architecture Core Refe
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Chapter 4 Instruction Pipeline and
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4.1.2 Instruction Unit e200z1 Power
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Figure 4-2. Pipeline Diagram 4.3.1
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Time Slot 1st LD inst. IFETCH DEC /
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4.5.1 Completion Serialization e200
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4.7 Instruction Timings e200z1 Powe
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Chapter 5 Interrupts and Exceptions
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Interrupt Type e200z1 Power Archite
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14 (46) 15 (47) 16:23 (48:55) 5.3 M
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23 (55) 24 (56) 25 (57) 26 (58) 27
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MSR UCLE 0 WE 0 CE 0 EE 0 PR 0 ESR
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5.7.5 External Input Interrupt (IVO
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Table 5-18 lists register settings
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Table 5-21 lists register settings
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21 22 3 23 24 25 Data Storage 1. Ac
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Chapter 6 Memory Management Unit 6.
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21:25 [53:57] 26:27 [58:59] 28:29 [
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6.5 Software Interface and TLB Inst
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6.5.4 TLB Invalidate (tlbivax) Inst
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6.7.2 MMU Control and Status Regist
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Table 6-10. MAS1—Descriptor Conte
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The MAS3 register is shown in Figur
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6.7.4 MAS Registers Summary The MAS
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6.9 Core Interface Operation for MM
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Chapter 7 Core Complex Interfaces T
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Address Bus Transfer Control Transf
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Table 7-1. External Interface Signa
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j_lsrl_regsel O 0 External LSRL reg
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p_sprnum[0:9] O — Global SPR addr
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7.3.4.1 Transfer Type (p_d_htrans[1
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Table 7-8. p_[d,i]_hprot[5:0] Prote
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B. E. Word @001 0 0 1 1 0 0 B. E. W
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0 1 1 0 1 x x Reserved 0 1 1 1 0 x
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7.3.12.2 Processor Halt Request (p_
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7.3.14.1 OnCE Enable (jd_en_once) e
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1 j_tdo_en is asserted when the TAP
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7.3.15.14 Register Select (j_gp_reg
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Clock 2 (C2): e200z1 Power Architec
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7.4.1.5 Read and Write Transfers Fi
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7.4.1.6 Misaligned Accesses e200z1
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Figure 7-15 illustrates functional
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Figure 7-15 illustrates functional
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m_clk p_htrans p_addr,p_hprot p_hsi
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m_clk p_tbclk p_tbdisable t_tbclk_h
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Chapter 8 Power Management 8.1 Powe
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Chapter 9 Debug Support This chapte
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9.2.1 Instruction Address Compare E
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9.2.5 Branch Taken Debug Event e200
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9.2.13 Unconditional Debug Event e2
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Table 9-1 provides bit definitions
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9.3.3.2 Debug Control Register 1 (D
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9.3.3.3 Debug Control Register 2 (D
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Table 9-4. DBCR3 Bit Definitions (c
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posted, but the counter value will
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Table 9-9 indicates the e200 OnCE r
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Table 9-11 provides a list of acces
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9.4.7.4 Debug Request During Waitin
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9.4.8.2 Control State Register (CTL
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IRStat5—IR Status Bit 5 IRStat6
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To single-step the CPU: e200z1 Powe
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. 9.7.2 Parallel Signature Status R
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Appendix A Register Summary Conditi
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e200 z1 0 Figure A-3. e200 Supervis
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0 e200z1 Power Architecture Core Re
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* Figure A-27. CPU Scan Chain Regis
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M A S 0 M A S 1 M A S 2 M A S 3 M A
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Appendix B Revision History This ap
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Glossary The glossary contains an a
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Copy-back operation. A cache operat
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Local access window. Mapping used t
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Physical medium attachment (PMA) su
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Set (n). A subdivision of a cache.
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A Alignment exception, 5-15 B Branc
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