E200Z1RM, e200z1 Power Architecture Ž Core - Reference Manual

Register Model
2.4.6 Exception Syndrome Register
The Exception Syndrome Register (ESR) provides a syndrome to differentiate between exceptions that can
generate the same interrupt type. e200 adds some implementation-specific bits to this register, as seen in
Figure 2-9.
The ESR fields are defined in Table 2-6.
Table 2-5. XER Field Descriptions
Bits Name Description
0
(32)
1
(33)
2
(34)
3:24
(35:56)
25:31
(57:63)
SO Summary Overflow (per Book E)
OV Overflow (per Book E)
CA Carry (per Book E)
— Reserved 1
Bytecnt 2
Preserved for lswi, lswx, stswi, stswx string instructions
1
These bits are not implemented, are read as zero, and writes are ignored.
2
These bits are implemented to support emulation of the string instructions.
0
PIL
PPR
PTR
FP
ST
0
DLK
ILK
AP
PUO
BO
PIE
e200z1 Power Architecture Core Reference Manual, Rev. 0
2-12 Freescale Semiconductor
0
EFP
0
VLEMI
0
MIF
XTE
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
SPR—62; Read/Write; Reset—0x0
Figure 2-9. Exception Syndrome Register (ESR)
Table 2-6. ESR Field Descriptions
Bit(s) Name Description Associated Interrupt Type
0:3
(32:35)
4
(36)
5
(37)
6
(38)
7
(39)
— Allocated 1
PIL Illegal Instruction exception Program
PPR Privileged Instruction exception Program
PTR Trap exception Program
FP Floating-point operation Alignment
Data Storage
Data TLB
Program
—