E200Z1RM, e200z1 Power Architecture Ž Core - Reference Manual

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Register Model Condition Register CR Count Register CTR Link Register XER LR XER General Registers SPR 9 SPR 8 SPR 1 Processor Control Registers Machine State MSR PVR Processor ID Context Control PIR SPR 286 1 Hardware Implementation Dependent Processor Version 1 HID0 SPR 1008 SPR 287 HID1 SPR 1009 CTXCR SPR 560 System Version ALTCTXCR SPR 568 1 SVR SPR 1023 Debug Control DBCR0 DBCR1 DBCR2 DBCR31 SPR 308 SPR 309 SPR 310 SPR 561 Debug Status DBSR SPR 304 Debug Counter1 DBCNT SPR 562 Debug Registers 2 Instruction Address Compare IAC1 IAC2 IAC3 IAC4 SUPERVISOR Mode Program Model SPRs General-Purpose Registers GPR0 GPR1 GPR31 SPR 312 SPR 313 SPR 314 SPR 315 Data Address Compare DAC1 SPR 316 DAC2 SPR 317 1—These e200-specific registers may not be supported by other PowerPC processors 2—Optional registers defined by the PowerPC. Book-E architecture. 3—Read-only registers. Exception Handling/Control Registers SPR General Save and Restore SPRG0 SPR 272 SRR0 SPRG1 SPR 273 SRR1 SPRG2 SPR 274 CSRR0 SPRG3 SPR 275 CSRR1 SPRG4 SPR 276 DSRR0 SPRG5 SPR 277 SPRG6 SPR 278 SPRG7 SPR 279 1 DSRR11 Interrupt Vector Prefix SPR 26 IVPR SPR 63 SPR 27 SPR 58 SPR 59 SPR 574 SPR 575 Exception Syndrome Register ESR SPR 62 User SPR USPRG0 SPR 256 Timers Time Base (writeonly) TBL SPR 284 TBU SPR 285 Control and Status TCR SPR 340 TSR SPR 336 MMU Assist 1 MAS0 MAS1 MAS2 MAS3 MAS4 MAS6 SPR 624 SPR 625 SPR 626 SPR 627 SPR 628 SPR 630 Machine Check Syndrome Register Data Exception Address Decrementer DEC SPR 22 DECAR SPR 54 Cache Registers Cache Configuration (Read-only) SPR 515 Figure 2-1. e200z1 Supervisor Mode Programmer’s Model SPRs e200z1 Power Architecture Core Reference Manual, Rev. 0 2-2 Freescale Semiconductor L1CFG0 MCSR SPR 572 DEAR SPR 61 BTB Control1 BTB Register BUCSR Memory Management Registers Process ID PID0 SPR 48 SPR 1013 Control & Configuration MMUCSR0 MMUCFG TLB0CFG TLB1CFG SPR 1012 SPR 1015 SPR 688 SPR 689
PSU Registers 1 PSU PSCR PSSR PSHR PSLR PSCTR PSUHR PSULR Supervisor Mode Program Model DCRs DCR 272 DCR 273 DCR 274 DCR 275 DCR 276 DCR 277 DCR 278 1 - These e200-specific registers may not be supported by other PowerPC processors. Figure 2-2. e200 Supervisor Mode Program Model Device Control Registers (DCRs) Condition Register Count Register CTR Link Register XER CR LR XER General Registers SPR 9 SPR 8 SPR 1 General-Purpose Registers GPR0 GPR1 GPR31 USER Mode Program Model Timers (Read only) Time Base TBL SPR 268 TBU SPR 269 Control Registers SPR General (Read-only) SPRG4 SPR 260 SPRG5 SPR 261 SPRG6 SPR 262 SPRG7 SPR 263 User SPR USPRG0 SPR 256 Figure 2-3. e200 User Mode Program Model e200z1 Power Architecture Core Reference Manual, Rev. 0 Cache Register (Read-only) Cache Configuration SPR 515 Register Model General purpose registers (GPRs) are accessed through instruction operands. Access to other registers can be explicit (by using instructions for that purpose such as Move to Special Purpose Register (mtspr) and Move from Special Purpose Register (mfspr) instructions) or implicit as part of the execution of an instruction. Some registers are accessed both explicitly and implicitly. Freescale Semiconductor 2-3 L1CFG0
Page 1 and 2: e200z1 Power Architecture Core Refe
Page 3 and 4: Contents Paragraph Number Title Con
Page 5 and 6: Contents Paragraph Number Title e20
Page 13 and 14: Figures Figure Number Title e200z1
Page 15 and 16: Figures Figure Number Title e200z1
Page 17 and 18: Tables Table Number Title e200z1 Po
Page 19 and 20: Tables Table Number Title e200z1 Po
Page 21 and 22: Chapter 1 e200z1 Overview 1.1 Overv
Page 27: Chapter 2 Register Model This secti
Page 35 and 36: 17 (49) 18 (50) 19 (51) 20 (52) 21
Page 39 and 40: 8 (40) 9 (41) 10 (42) 11 (43) 12 (4
Page 43 and 44: 2.4.9 Timer Status Register (TSR) e
Page 45 and 46: 14 ICR Interrupt Inputs Clear Reser
Page 47 and 48: 2.4.13 Branch Unit Control and Stat
Page 49 and 50: Table 2-14. Additional Synchronizat
Page 51 and 52: Mnemonic Name Table 2-15. Special P
Page 53 and 54: Table 2-16. Reset Settings for e200
Page 55 and 56: Chapter 3 Instruction Model This ch
Page 57 and 58: 3.5 Memory Access Alignment Support
Page 63 and 64: 3.12.1 Instruction Index Sorted by
Page 65 and 66: Format Primary (Inst 0:5) Opcode e2
Page 67 and 68: Format Primary (Inst 0:5) Opcode X
Page 69 and 70: Format Primary (Inst 0:5) Opcode X
Page 71 and 72: Format Primary (Inst 0:5) Opcode XL
Page 73 and 74: Format Primary (Inst 0:5) Opcode Ta
Page 75 and 76: Format Primary (Inst0:5) Opcode Ext
Page 77 and 78: Format Primary (Inst0:5) Opcode Ext
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Format Primary (Inst0:5) Opcode Ext
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e200z1 Power Architecture Core Refe
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Chapter 4 Instruction Pipeline and
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4.1.2 Instruction Unit e200z1 Power
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Figure 4-2. Pipeline Diagram 4.3.1
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Time Slot 1st LD inst. IFETCH DEC /
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4.5.1 Completion Serialization e200
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4.7 Instruction Timings e200z1 Powe
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Chapter 5 Interrupts and Exceptions
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Interrupt Type e200z1 Power Archite
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14 (46) 15 (47) 16:23 (48:55) 5.3 M
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23 (55) 24 (56) 25 (57) 26 (58) 27
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MSR UCLE 0 WE 0 CE 0 EE 0 PR 0 ESR
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5.7.5 External Input Interrupt (IVO
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Table 5-18 lists register settings
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Table 5-21 lists register settings
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21 22 3 23 24 25 Data Storage 1. Ac
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Chapter 6 Memory Management Unit 6.
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21:25 [53:57] 26:27 [58:59] 28:29 [
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6.5 Software Interface and TLB Inst
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6.5.4 TLB Invalidate (tlbivax) Inst
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6.7.2 MMU Control and Status Regist
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Table 6-10. MAS1—Descriptor Conte
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The MAS3 register is shown in Figur
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6.7.4 MAS Registers Summary The MAS
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6.9 Core Interface Operation for MM
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Chapter 7 Core Complex Interfaces T
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Address Bus Transfer Control Transf
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Table 7-1. External Interface Signa
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j_lsrl_regsel O 0 External LSRL reg
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p_sprnum[0:9] O — Global SPR addr
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7.3.4.1 Transfer Type (p_d_htrans[1
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Table 7-8. p_[d,i]_hprot[5:0] Prote
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B. E. Word @001 0 0 1 1 0 0 B. E. W
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0 1 1 0 1 x x Reserved 0 1 1 1 0 x
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7.3.12.2 Processor Halt Request (p_
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7.3.14.1 OnCE Enable (jd_en_once) e
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1 j_tdo_en is asserted when the TAP
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7.3.15.14 Register Select (j_gp_reg
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Clock 2 (C2): e200z1 Power Architec
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7.4.1.5 Read and Write Transfers Fi
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7.4.1.6 Misaligned Accesses e200z1
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Figure 7-15 illustrates functional
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Figure 7-15 illustrates functional
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m_clk p_htrans p_addr,p_hprot p_hsi
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m_clk p_tbclk p_tbdisable t_tbclk_h
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Chapter 8 Power Management 8.1 Powe
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Chapter 9 Debug Support This chapte
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9.2.1 Instruction Address Compare E
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9.2.5 Branch Taken Debug Event e200
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9.2.13 Unconditional Debug Event e2
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Table 9-1 provides bit definitions
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9.3.3.2 Debug Control Register 1 (D
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9.3.3.3 Debug Control Register 2 (D
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Table 9-4. DBCR3 Bit Definitions (c
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posted, but the counter value will
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Table 9-9 indicates the e200 OnCE r
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Table 9-11 provides a list of acces
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9.4.7.4 Debug Request During Waitin
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9.4.8.2 Control State Register (CTL
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IRStat5—IR Status Bit 5 IRStat6
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To single-step the CPU: e200z1 Powe
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. 9.7.2 Parallel Signature Status R
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Appendix A Register Summary Conditi
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e200 z1 0 Figure A-3. e200 Supervis
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0 e200z1 Power Architecture Core Re
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* Figure A-27. CPU Scan Chain Regis
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M A S 0 M A S 1 M A S 2 M A S 3 M A
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Appendix B Revision History This ap
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Glossary The glossary contains an a
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Copy-back operation. A cache operat
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Local access window. Mapping used t
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Physical medium attachment (PMA) su
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Set (n). A subdivision of a cache.
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A Alignment exception, 5-15 B Branc
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E200Z1RM, e200z1 Power Architecture Ž Core - Reference Manual

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