E200Z1RM, e200z1 Power Architecture Ž Core - Reference Manual

Register Model
The TCR fields are defined in Table 2-8
Table 2-8. Timer Control Register Field Descriptions
Bits Name Description
0:1
(32:33)
2:3
(34:35)
4
(36)
5
(37)
6:7
(38:39)
8
(40)
9
(41)
10
(42)
11:14
(43:46)
15:18
(47:50)
19:31
(51:63)
WP Watchdog Timer Period
When concatenated with WPEXT, specifies one of 64 bit locations of the time base used to signal a
watchdog timer exception on a transition from 0 to 1.
TCRwpext[0–3],TCRwp[0–1] == 6’b000000 selects TBU[0]
TCRwpext[0–3],TCRwp[0–1] == 6’b111111 selects TBL[31]
WRC Watchdog Timer Reset Control
00 No Watchdog Timer reset will occur
01 Force processor checkstop on second time-out of Watchdog Timer
10 Assert processor reset output (p_resetout_b) on second time-out of Watchdog Timer
11 Reserved
TCR[WRC] resets to 0b00. This field may be set by software, but cannot be cleared by software (except
by a software-induced reset). Once written to a non-zero value, this field may no longer be altered by
software.
WIE Watchdog Timer Interrupt Enable
DIE Decrementer Interrupt Enable
FP Fixed-Interval Timer Period - When concatenated with FPEXT, specifies one of 64 bit locations of the time
base used to signal a fixed-interval timer exception on a transition from 0 to 1.
TCR fpext [0–3],TCR fp [0–1] == 6’b000000 selects TBU[0]
TCR fpext [0–3],TCR fp [0–1] == 6’b111111 selects TBL[31]
FIE Fixed-Interval Timer Interrupt Enable
ARE Auto-reload Enable
— Reserved 1
WPEXT Watchdog Timer Period Extension (see above description for WP)
These bits get prepended to the TCR WP bits to allow selection of the one of the 64 Time Base bits used
to signal a Watchdog Timer exception.
tb 0:63 ← TBU 0:31 || TBL 0:31
wp ← TCR WPEXT || TCR WP
tb_wp_bit ← tb wp
FPEXT Fixed-Interval Timer Period Extension (see above description for FP)
These bits get prepended to the TCR FP bits to allow selection of the one of the 64 Time Base bits used
to signal a Fixed-Interval Timer exception.
tb 0:63 ← TBU 0:31 || TBL 0:31
fp ← TCR FPEXT || TCR FP
tb_fp_bit ← tb fp
— Reserved 1
1 These bits are not implemented and should be written with zero for future compatibility.
e200z1 Power Architecture Core Reference Manual, Rev. 0
2-16 Freescale Semiconductor