E200Z1RM, e200z1 Power Architecture Ž Core - Reference Manual

Contents
Paragraph
Number Title
e200z1 Power Architecture Core Reference Manual, Rev. 0
Page
Number
5.7.6 Alignment Interrupt (IVOR5).................................................................................... 5-15
5.7.7 Program Interrupt (IVOR6) ....................................................................................... 5-16
5.7.8 Floating-Point Unavailable Interrupt (IVOR7).......................................................... 5-17
5.7.9 System Call Interrupt (IVOR8).................................................................................. 5-18
5.7.10 Auxiliary Processor Unavailable Interrupt (IVOR9)................................................. 5-18
5.7.11 Decrementer Interrupt (IVOR10) .............................................................................. 5-18
5.7.12 Fixed-Interval Timer Interrupt (IVOR11).................................................................. 5-19
5.7.13 Watchdog Timer Interrupt (IVOR12) ........................................................................ 5-20
5.7.14 Data TLB Error Interrupt (IVOR13) ......................................................................... 5-20
5.7.15 Instruction TLB Error Interrupt (IVOR14)................................................................ 5-21
5.7.16 Debug Interrupt (IVOR15) ........................................................................................ 5-22
5.7.17 System Reset Interrupt............................................................................................... 5-24
5.8 Exception Recognition and Priorities ............................................................................ 5-26
5.8.1 Exception Priorities.................................................................................................... 5-27
5.9 Interrupt Processing ....................................................................................................... 5-29
5.9.1 Enabling and Disabling Exceptions........................................................................... 5-30
5.9.2 Returning from an Interrupt Handler ......................................................................... 5-31
5.10 Process Switching.......................................................................................................... 5-32
Chapter 6
Memory Management Unit
6.1 Overview.......................................................................................................................... 6-1
6.2 Effective to Real Address Translation ............................................................................. 6-1
6.2.1 Effective Addresses ..................................................................................................... 6-1
6.2.2 Address Spaces ............................................................................................................ 6-1
6.2.3 Process ID.................................................................................................................... 6-2
6.2.4 Translation Flow .......................................................................................................... 6-2
6.2.5 Permissions .................................................................................................................. 6-4
6.3 Translation Lookaside Buffer .......................................................................................... 6-5
6.4 Configuration Information............................................................................................... 6-6
6.4.1 MMU Configuration Register (MMUCFG) ................................................................ 6-6
6.4.2 TLB0 Configuration Register (TLB0CFG) ................................................................. 6-7
6.4.3 TLB1 Configuration Register (TLB1CFG) ................................................................. 6-8
6.5 Software Interface and TLB Instructions......................................................................... 6-9
6.5.1 TLB Read Entry Instruction (tlbre) ............................................................................. 6-9
6.5.2 TLB Write Entry Instruction (tlbwe) ......................................................................... 6-10
6.5.3 TLB Search Instruction (tlbsx) .................................................................................. 6-10
6.5.4 TLB Invalidate (tlbivax) Instruction.......................................................................... 6-11
6.5.5 TLB Synchronize Instruction (tlbsync) ..................................................................... 6-11
6.6 TLB Operations ............................................................................................................. 6-12
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